# DRV8220DRLR

**Texas Instruments** · Motor Driver ICs · SOT-563

DRV8220DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN1 | input | H-bridge control input (PWM interface) with an internal pulldown resistor; see Section 8.3.2. |
| 2 | IN2 | input | H-bridge control input (PWM interface) with an internal pulldown resistor; see Section 8.3.2. |
| 3 | GND | power_in | Device ground; connect to system ground. |
| 4 | OUT2 | output | H-bridge output; connect to the motor or other load. |
| 5 | VM | power_in | Motor power supply, 4.5 V to 18 V; bypass to GND with a 0.1-µF ceramic capacitor plus sufficient bulk capacitance rated for VM. |
| 6 | OUT1 | output | H-bridge output; connect to the motor or other load. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-563 |
| Category | Power Supply Chip |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply pin voltage | VM | -0.5 |  | 20 | V | VM | 5 |
| Power supply transient voltage ramp | VM | 0 |  | 2 | V/µs | VM | 5 |
| Logic pin voltage |  | -0.5 |  | 5.75 | V | INx, nSLEEP, IN1/PH, IN2/EN | 5 |
| Ambient temperature | TA | -40 |  | 125 | °C |  | 5 |
| Junction temperature | TJ | -40 |  | 150 | °C |  | 5 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 5 |
| ESD HBM | V(ESD) | -2000 |  | 2000 | V | Human body model, ANSI/ESDA/JEDEC JS-001 | 5 |
| ESD CDM | V(ESD) | -500 |  | 500 | V | Charged device model, JESD22-C101 | 5 |
| Motor power supply voltage | VVM | 4.5 |  | 18 | V | VM | 5 |
| Logic pin voltage | VIN | 0 |  | 5.5 | V | INx, nSLEEP, IN1/PH, IN2/EN, MODE | 5 |
| PWM frequency | fPWM | 0 |  | 100 | kHz | INx, IN1/PH, IN2/EN | 5 |
| Peak output current | IOUT | 0 |  | 1.76 | A | OUTx | 5 |
| Operating ambient temperature | TA | -40 |  | 125 | °C |  | 5 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 152.4 |  | °C/W | DRL (SOT563), 6 pins | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 63.6 |  | °C/W | DRL (SOT563) | 5 |
| Junction-to-board thermal resistance | RθJB |  | 39.1 |  | °C/W | DRL (SOT563) | 5 |
| Junction-to-top characterization parameter | ΨJT |  | 2 |  | °C/W | DRL (SOT563) | 5 |
| Junction-to-board characterization parameter | ΨJB |  | 38.7 |  | °C/W | DRL (SOT563) | 5 |
| VM active mode current | IVM |  | 1.5 | 2 | mA | IN1 = 0 V, IN2 = 3.3 V | 6 |
| VM sleep mode current | IVMQ |  | 960 |  | nA | Sleep mode, VVM = 12 V, TJ = 27°C | 6 |
| Turnon time | tWAKE |  |  | 65 | µs | Sleep mode to active mode delay | 6 |
| Autosleep turnoff time | tAUTOSLEEP | 0.9 |  | 2.6 | ms | Active mode to autosleep mode delay, nSLEEP = 3.3 V | 6 |
| Turnoff time | tSLEEP |  |  | 1 | µs | Active mode to sleep mode delay, nSLEEP = 0 V | 6 |
| Input logic low voltage | VIL | 0 |  | 0.35 | V |  | 6 |
| Input logic high voltage | VIH | 1.45 |  | 5.5 | V |  | 6 |
| Input logic hysteresis | VHYS |  | 49 |  | mV |  | 6 |
| Input logic low current | IIL | -1 |  | 1 | µA | VI = 0 V | 6 |
| Input logic high current, IN1/EN, IN2/PH | IIH |  | 20 | 50 | µA | VI = 3.3 V | 6 |
| Input logic high current, nSLEEP | IIH_nSLEEP |  | 60 | 100 | µA | VI = 3.3 V, active mode | 6 |
| Input pulldown resistance, IN1/EN, IN2/PH | RPD |  | 100 |  | kΩ | To GND | 6 |
| Tri-level input logic low voltage | VTIL | 0 |  | 0.22 | V | max is 0.22 × VnSLEEP (V) | 6 |
| High-side MOSFET on resistance | RDS(on)_HS |  | 500 |  | mΩ | IO = 0.2 A | 6 |
| Low-side MOSFET on resistance | RDS(on)_LS |  | 500 |  | mΩ | IO = -0.2 A | 6 |
| Body diode forward voltage | VSD |  |  | 1 | V | IO = -0.5 A | 6 |
| Output rise time | tRISE |  |  | 150 | ns | VOUTx rising from 10% to 90% of VVM | 6 |
| Output fall time | tFALL |  |  | 150 | ns | VOUTx falling from 90% to 10% of VVM | 6 |
| Input to output propagation delay | tPD |  |  | 135 | ns | Input crosses 0.8 V to VOUTx = 0.1×VVM, IO = 1 A | 6 |
| Output dead time | tDEAD |  | 500 |  | ns | Internal dead time | 6 |
| VM supply UVLO rising | VUVLO |  |  | 4.5 | V | Supply rising | 7 |
| VM supply UVLO falling | VUVLO | 3.7 |  |  | V | Supply falling | 7 |
| Supply UVLO hysteresis | VUVLO_HYS |  | 325 |  | mV | Rising to falling threshold | 7 |
| Overcurrent protection trip point | IOCP | 1.76 |  |  | A |  | 7 |
| Overcurrent protection deglitch time | tOCP |  | 4.2 |  | µs |  | 7 |
| Overcurrent protection retry time | tRETRY |  | 1.7 |  | ms |  | 7 |
| Thermal shutdown temperature | TTSD | 153 |  | 193 | °C |  | 7 |
| Thermal shutdown hysteresis | THYS |  | 22 |  | °C |  | 7 |

## CAD (KiCad official)

- Symbol: `DRV8220DRLR`
- Footprint: `Package_TO_SOT_SMD:SOT-563`
- 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files: `drv8220drlr-etched.step` / `drv8220drlr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8220drlr.step` / `drv8220drlr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/drv8220.pdf) (46 pp, sha256 `d3b7079b688e1498`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/drv8220drlr-datasheet.pdf)