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DRV8212DRLR

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Texas Instruments Brushed DC Motor Drivers, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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DRV8212DRLR

Texas Instruments · Brushed DC Motor Drivers · SOT-563

DRV8212DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1 input H-bridge PWM control input for OUT1/OUT2 in the DRL variant, with an internal pulldown resistor and a recommended logic input range of 0 V to 5.5 V (absolute maximum 5.75 V).
2 IN2 input H-bridge PWM control input for OUT1/OUT2 in the DRL variant, with an internal pulldown resistor and a recommended logic input range of 0 V to 5.5 V (absolute maximum 5.75 V).
3 GND power_in Device ground that must be connected to system ground.
4 OUT2 output H-bridge output that connects to the motor or other load.
5 VM power_in Motor power supply, rated 1.65 V to 11 V for the DRL package, to be bypassed to GND with a 0.1-µF ceramic capacitor plus sufficient bulk capacitance rated for VM.
6 OUT1 output H-bridge output that connects to the motor or other load.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-563
Category Motor Driver ICs
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply pin voltage VM -0.5 12 V 5
Power supply transient voltage ramp VM 0 2 V/µs 5
Logic pin voltage INx, IN1/PH, IN2/EN -0.5 5.75 V 5
Ambient temperature TA -40 125 °C 5
Junction temperature TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
Motor power supply voltage, DRL VVM 1.65 11 V 5
Logic pin voltage INx, IN1/PH, IN2/EN, MODE VIN 0 5.5 V 5
PWM frequency INx, IN1/PH, IN2/EN fPWM 0 100 kHz 5
Peak output current OUTx IOUT 0 4 A Power dissipation and thermal limits must be observed (table footnote 1) 5
Operating ambient temperature TA -40 125 °C 5
Operating junction temperature TJ -40 150 °C 5
VM active mode current IVM 6 11 mA IN1 = 0 V, IN2 = 3.3 V 6
VM sleep mode current IVMQ 5 80 nA INx = 0 V, after waiting tsleep, VVM = 5 V, TJ = 27°C 6
Autosleep turnoff time tAUTOSLEEP 0.9 2.6 ms Active mode to autosleep mode delay 6
Input logic low voltage VIL 0 0.4 V 6
Input logic high voltage VIH 1.45 5.5 V 6
Input logic low current IIL -1 1 µA VI = 0 V 6
Input logic high current IIH 20 50 µA VI = 3.3 V 6
Supply UVLO threshold, VM rising VUVLO,VM 1.65 V Supply rising 7
Supply UVLO threshold, VM falling VUVLO,VM 1.3 V Supply falling 7
Thermal shutdown temperature TTSD 153 193 °C 7
Input pulldown resistance RPD 100 kΩ To GND 6
High-side MOSFET on resistance RDS(on)_HS 140 mΩ IO = 0.2 A 6
Low-side MOSFET on resistance RDS(on)_LS 140 mΩ IO = -0.2 A 6
Body diode forward voltage VSD 1 V IO = -1.5 A 6
Output rise time tRISE 150 ns VOUTx rising from 10% to 90% of VVM 7
Output fall time tFALL 150 ns VOUTx falling from 90% to 10% of VVM 7
Input to output propagation delay tPD 135 ns Input crosses 0.8 V to VOUTx = 0.1×VVM, IO = 1 A 7
Output dead time tDEAD 500 ns Internal dead time 7
Leakage current into OUTx IOUT 186 µA OUTx is Hi-Z, RL = 20 Ω to VM 7
Leakage current into OUTx IOUT -3 nA OUTx is Hi-Z, RL = 20 Ω to GND 7
Supply UVLO hysteresis VUVLO_HYS 80 mV Rising to falling threshold 7
Supply undervoltage deglitch time tUVLO 3.8 µs VVM falling (DRL) to OUTx disabled 7
Overcurrent protection trip point IOCP 4 A 7
Overcurrent protection deglitch time tOCP 4.2 µs 7
Overcurrent protection retry time tRETRY 1.7 ms 7
Thermal shutdown hysteresis THYS 22 °C 7
Turn-on time tWAKE 100 µs Sleep mode to active mode delay 6
Input logic hysteresis VHYS 49 mV 6
Junction-to-ambient thermal resistance RθJA 138.5 °C/W DRL (SOT563), 6 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 46.4 °C/W DRL (SOT563), 6 pins 5
Junction-to-board thermal resistance RθJB 25.8 °C/W DRL (SOT563), 6 pins 5
Junction-to-top characterization parameter ΨJT 1.3 °C/W DRL (SOT563), 6 pins 6
Junction-to-board characterization parameter ΨJB 25.6 °C/W DRL (SOT563), 6 pins 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 21.1 °C/W DRL (SOT563), 6 pins 6

CAD (KiCad official)

  • Symbol: DRV8212DRLR
  • Footprint: Package_TO_SOT_SMD:SOT-563
  • 3D model: SOT-563 (KiCad packages3D, STEP)
  • 3D model files: drv8212drlr-etched.step / drv8212drlr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8212drlr.step / drv8212drlr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (48 pp, sha256 20ff22c1cc9d645e, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF