DRV602PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	+INR	input	Right channel OPAMP positive (non-inverting) input.
2	-INR	input	Right channel OPAMP negative (inverting) input.
3	OUTR	output	Right channel OPAMP output.
4	SGND	power_in	Signal ground for the device.
5	EN	input	Active-high enable input; VIH is 60% of VDD minimum and VIL is 40% of VDD maximum, and it should be held low until the input ac-coupling capacitors are charged for pop-free power-up.
6	PVSS	power_out	Negative supply voltage generated by the internal charge pump; its capacitor must be at least equal to the charge pump flying capacitor (1 µF typical).
7	CN	bidirectional	Charge pump flying capacitor negative terminal; 1 µF is typical.
8	CP	bidirectional	Charge pump flying capacitor positive terminal; 1 µF is typical.
9	PVDD	power_in	Positive supply input (VDD range 3 V to 5.5 V); a low-ESR ceramic decoupling capacitor, typically 1 µF, should be placed as close as possible to this lead.
10	PGND	power_in	Power ground for the device.
11	NC	unconnected	No internal connection.
12	OUTL	output	Left channel OPAMP output.
13	-INL	input	Left channel OPAMP negative (inverting) input.
14	+INL	input	Left channel OPAMP positive (non-inverting) input.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-14
Category	Amplifiers/Comparators
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DC supply voltage	VDD	3	3.3	5.5	V	DC supply voltage	3
High-level input voltage, EN	VIH	60			% of VDD		3
Low-level input voltage, EN	VIL			40	% of VDD		3
Operating free-air temperature	TA	-40		85	°C		3
Supply voltage, VDD to GND	VDD	-0.3		5.5	V	Over operating free-air temperature range	3
Minimum load impedance	RL	600			Ω	Printed as > 600 Ω	3
EN to GND		-0.3			V	Upper limit printed as VDD + 0.3 V	3
Maximum operating junction temperature range	TJ	-40		150	°C		3
Storage temperature range	Tstg	-40		150	°C		3
IEC contact ESD protection, output pins		-8		8	kV	IEC contact ESD per IEC6100-4-2, on output pins measured on DRV602EVM	3
Junction-to-case thermal resistance	θJC		35		°/W		3
Junction-to-ambient thermal resistance	θJA		115		°/W	JEDEC high-K test PCB	3
Junction-to-ambient thermal resistance (low-K PCB)	θJA		185		°/W	JEDEC low-K test PCB	3
Power rating				870	mW	TA ≤ 25°C; junction temperature 125°C	3
Power rating				348	mW	TA ≤ 70°C; junction temperature 125°C	3
Output offset voltage	/VOS/			5	mV	VDD = 3 V to 5 V, voltage follower, gain = 1	3
Supply rejection ratio	PSRR	88			dB	VDD = 3.3 V to 5 V	3
High-level output voltage	VOH	3.1			V	VDD = 3.3 V, RL = 2.5 kΩ	3
Low-level output voltage	VOL			-3.05	V	VDD = 3.3 V, RL = 2.5 kΩ	3
High-level input current (EN)	/IIH/			1	µA	VDD = 5 V, VI = VDD	3
Low-level input current (EN)	/IIL/			1	µA	VDD = 5 V, VI = 0 V	3
Supply current, no load, EN = VDD	IDD		8	11	mA	VDD = 3.3 V, no load, EN = VDD	3
Supply current, no load, EN = VDD	IDD		12.5	20	mA	VDD = 5 V, no load, EN = VDD	3
Supply current, shutdown mode	IDD			2	mA	Shutdown mode, VDD = 3 V to 5 V	3
Output voltage (outputs in phase)	VO		2.05		Vrms	THD = 1%, VDD = 3.3 V, f = 1 kHz	4
Output voltage (outputs in phase)	VO		3.01		Vrms	THD = 1%, VDD = 5 V, f = 1 kHz	4
Total harmonic distortion plus noise	THD+N		0.01		%	VO = 2 Vrms, f = 1 kHz	4
Total harmonic distortion plus noise	THD+N		0.05		%	VO = 2 Vrms, f = 6.8 kHz	4
Crosstalk			-100		dB	VO = 2 Vrms, f = 1 kHz	4
Output current limit	IO		20		mA	VDD = 3.3 V	4
Input resistor range	RIN	1	10	47	kΩ		4
Feedback resistor range	Rfb	4.7	20	100	kΩ		4
Slew rate			4.5		V/ms		4
Maximum capacitive load				220	pF		4
Noise output voltage	VN			15	mVrms	A-weighted, BW 20 Hz-22 kHz	4
Signal to noise ratio	SNR	102			dB	VO = 2 Vrms, THD+N = 0.1%, 22 kHz BW, A-weighted	4
Unity gain bandwidth	GBW		8		MHz		4
Open-loop voltage gain	AVO		150		dB		4
Charge pump frequency	Fcp	225	450	675	kHz		4

CAD (KiCad official)

Symbol: DRV602PWR
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: drv602pwr-etched.step / drv602pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv602pwr.step / drv602pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (18 pp, sha256 d5b93e593d3d3f0b, retrieved 2026-11-11, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DRV602PWR

Verified DRV602PWR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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