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docs drv11873pwpr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
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drv11873pwpr-etched.fit.json drv11873pwpr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
drv11873pwpr-etched.glb drv11873pwpr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
drv11873pwpr-etched.step drv11873pwpr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
drv11873pwpr.glb Publish 0.1.0 · Ray
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package.json drv11873pwpr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
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README.md Initial commit: component/drv11873pwpr · Ray

DRV11873PWPR

Texas Instruments · Brushless DC (BLDC) Motor Driver · HTSSOP-16-EP

DRV11873PWPR from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FS input Motor parameter adjustment pin; pull low for a lower-speed motor and pull high for a high-speed motor (state latched only at power-up).
2 FG output Open-drain frequency generator output whose period equals 6 electrical states, used to indicate motor speed/phase; requires external pull-up resistor (100 kΩ or higher) to V5 or VCC.
3 RD output Open-drain lock-detect output that is pulled high through an external pull-up resistor to VCC or 5 V when the motor lock condition is detected.
4 VCP power_out Charge pump output that supplies the boosted gate-drive voltage for the internal high-side MOSFETs.
5 CPP passive Charge pump conversion terminal; connects to an external flying capacitor together with CPN for the internal charge pump.
6 CPN passive Charge pump conversion terminal; connects to an external flying capacitor together with CPP for the internal charge pump.
7 W output Phase W motor drive output from the integrated power MOSFET half-bridge, rated for up to 1.5 A continuous / 2 A peak drive current.
8 GND power_in Ground pin; must be connected to system ground and to the thermal pad for proper operation and heat dissipation.
9 V power_in Phase V motor drive output from the integrated power MOSFET half-bridge, rated for up to 1.5 A continuous / 2 A peak drive current.
10 U output Phase U motor drive output from the integrated power MOSFET half-bridge, rated for up to 1.5 A continuous / 2 A peak drive current.
11 VCC power_in Input supply voltage for the motor and chip, recommended operating range 5 V to 16 V.
12 V5 power_out 5-V LDO regulator output capable of sourcing up to 20 mA for external use; requires a 2.2-µF ceramic decoupling capacitor to ground.
13 COM input Motor common terminal input used as the BEMF reference; if the motor has no common wire, a simulated COM node must be created with three resistors in a wye configuration.
14 CS input Overcurrent threshold set-up pin; an external resistor to ground sets the current limit per Ilimit(A)=6600/RCS(Ω), valid for 500 mA < Ilimit < 2000 mA; shorting to ground disables overcurrent protection.
15 FR input Forward/reverse rotation control pin; set high for reverse rotation, set low or floating for forward rotation (latched at power-up, resettable via a PWMIN low pulse of defined duration).
16 PWMIN input PWM input pin (7 kHz to 100 kHz) used to set motor speed; internally pulled up to V5 and converted to a fixed switching frequency (125 kHz with FS high, 62.5 kHz with FS low) on the MOSFET driver.
17 PowerPAD power_in Exposed thermal pad (PowerPAD) on the package underside; must be connected to GND copper with vias for heat dissipation per the layout guidelines.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-16-EP
Category Motor Driver ICs
Pins 17

CAD (KiCad official)

  • Symbol: DRV11873PWPR
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: drv11873pwpr-etched.step / drv11873pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv11873pwpr.step / drv11873pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 7e6dbc06ff3f5d1f, retrieved 2026-09-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF