component
DRV104PWP
Public Made by Adomby adom
Texas Instruments Power Distribution Switches, HTSSOP-14-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDRV104PWP
Texas Instruments · Power Distribution Switches · HTSSOP-14-EP
DRV104PWP from Texas Instruments, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Duty Cycle Adj | input | Analog input connected to comparator input and 2.75×IREF current source that linearly sets PWM duty cycle; active range 1.3V to 3.9V corresponds to 10% to 90% duty cycle. |
| 2 | Delay Adj | input | Controls duration of initial 100% duty cycle before PWM mode through charge to 2.6V threshold comparator; internally driven by 15µA current source from VS; floating pin limits delay to 18µs minimum. |
| 3 | Osc Freq Adj | input | External resistor to ground sets PWM oscillator frequency from 500Hz to 100kHz by controlling IREF current source; in slave mode sets current limit reset frequency. |
| 4 | Master | input | Logic input that selects master mode (floating/high, pulls to 5V internally via 15µA source) making SYNC an output, or slave mode (low) making SYNC an input. |
| 5 | BOOT | passive | Bootstrap capacitor connection node (>100pF, typically 470pF) between this pin and power output that supplies VGS charge to gate drive the high-side DMOS transistor. |
| 6 | OUT1 | output | High-side power output from DMOS source connected to VPS with low on-resistance (0.45Ω typical), saturation voltage 0.45V to 0.65V at 1A, current-limited to 1.2A typical. |
| 7 | OUT2 | output | High-side power output from DMOS source connected to VPS with low on-resistance (0.45Ω typical), saturation voltage 0.45V to 0.65V at 1A, current-limited to 1.2A typical. |
| 8 | VPS1 | power_in | Load power-supply connection to drain of power DMOS transistor; voltage may exceed VS by 5V maximum but must not exceed 37V practical limit or 40V absolute maximum. |
| 9 | VPS2 | power_in | Load power-supply connection to drain of power DMOS transistor; voltage may exceed VS by 5V maximum but must not exceed 37V practical limit or 40V absolute maximum. |
| 10 | +VS | power_in | Logic and control circuit power supply with operating range 8V to 32V; quiescent current 0.6mA to 1mA at 24V nominal supply. |
| 11 | GND | power_in | Ground reference for all logic and control circuits; does not carry load current when power DMOS device is switched on. |
| 12 | SYNC | bidirectional | Synchronization output in master mode (0V to 4.2V, 100µA source with 1kΩ output resistance) providing copy of power output state; input in slave mode with 2V switching threshold controlling power output. |
| 13 | Status OK Flag | output | Open-drain active-low flag output that indicates over-temperature fault (junction ≥160°C) or over-current condition; requires pull-up resistor and sinks up to 10mA typical. |
| 14 | Input | input | TTL-compatible logic input with 1.8V switching threshold; device enabled when driven above 2.2V, disabled below 1.2V; input current typically 1µA at all logic levels. |
| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-14-EP |
| Category | Power Management (PMIC) |
| Pins | 15 |
CAD (KiCad official)
- Symbol:
DRV104PWP - Footprint:
Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-14-EP (KiCad packages3D, STEP)
- 3D model files:
drv104pwp-etched.step/drv104pwp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv104pwp.step/drv104pwp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (25 pp, sha256
e259add3a2ce23ae, retrieved 2026-09-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).