component
DRV103U
Public Made by Adomby adom
Texas Instruments Power Distribution Switches, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
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| viewers | |
| drv103u-etched.fit.json | |
| drv103u-etched.glb | |
| drv103u-etched.step | |
| drv103u.glb | |
| drv103u.kicad_mod | |
| drv103u.kicad_sym | |
| drv103u.lbr | |
| drv103u.step | |
| package.json | |
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| README.md |
DRV103U
Texas Instruments · Power Distribution Switches · SOIC-8
DRV103U from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DUTY CYCLE ADJ | passive | Connects internally to a comparator input and a 2.75×IREF current source from VS; a resistor, analog voltage, or D/A output from 1.3V to 3.9V sets PWM duty cycle from about 10% (1.5V) to 90% (3.56V). |
| 2 | DELAY ADJ | passive | Sets the initial 100% duty-cycle (DC) time before PWM mode begins via an external capacitor to ground; internally driven by a 3µA current source from VS into a 2.6V threshold comparator, floating gives ~18µs delay and tying to +5V gives <1µs delay. |
| 3 | OSC FREQ ADJ | passive | A resistor to ground sets the reference current IREF and programs the internal PWM oscillator frequency over a range of 500Hz to 100kHz. |
| 4 | GND | power_in | System ground return; carries the 0.4mA typical quiescent current plus the full load current when the output DMOS is switched on. |
| 5 | OUT | output | Drain of the low-side power DMOS switch (source grounded), rated up to 1.5A in this SO-8 package, with 0.5Ω typical on-resistance, slew-rate-limited rise/fall and an internal ESD clamp diode (not for use as a flyback diode) to +VS. |
| 6 | +VS | power_in | Power supply input, operating range +8V to +32V (absolute maximum +40V), must be equal to or greater than the load supply voltage. |
| 7 | STATUS OK FLAG | output | Open-drain, active-LOW fault flag (normally HIGH) indicating over-temperature or over-current shutdown; requires an external pull-up and can sink up to 10mA (internally current-limited). |
| 8 | INPUT | input | TTL-compatible digital control input; a voltage of +2.2V to +5.5V enables the output, 0V to +1.2V disables it, with switching threshold ~1.7V and input current ~10nA; must not be tied directly to +VS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
DRV103U - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
drv103u-etched.step/drv103u-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv103u.step/drv103u.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (27 pp, sha256
6449d7cec62e2573, retrieved 2026-09-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).