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Contents

README

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DRTR5V0U2SR-7

Diodes Incorporated · ESD Protection Devices · SOT-143

DRTR5V0U2SR-7 from Diodes Incorporated, in a SOT-143. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.

Pinout

Pin Name Type Function
1 GND power_in Ground reference for the TVS array; I/O-to-GND capacitance is 1.0pF typical (1.5pF max) and reverse breakdown of 6.0V to 9.0V at 1mA is measured from pin 4 to pin 1.
2 I/O1 bidirectional ESD-protected channel 1 (IEC 61000-4-2 ±8kV contact, ±15kV air) with 1.0pF typical capacitance to GND and 100nA max leakage at VR=3V.
3 I/O2 bidirectional ESD-protected channel 2 (IEC 61000-4-2 ±8kV contact, ±15kV air) with 1.0pF typical capacitance to GND and 100nA max leakage at VR=3V.
4 VCC power_in Positive supply/rail clamp reference pin with reverse standoff voltage of 5.5V max and breakdown of 6.0V to 9.0V at 1mA measured from pin 4 to pin 1.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-143
Category Circuit Protection
Pins 4

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Peak Pulse Current IPP 5 A 8/20µs, Per Figure 3 2
ESD Protection, Contact Discharge VESD_Contact -8 8 kV Standard IEC 61000-4-2 2
ESD Protection, Air Discharge VESD_Air -15 15 kV Standard IEC 61000-4-2 2
Power Dissipation PD 400 mW Device mounted on FR-4 PCB pad layout (2oz copper), Note 5 2
Thermal Resistance, Junction to Ambient RθJA 310 °C/W Device mounted on FR-4 PCB pad layout (2oz copper), Note 5 2
Operating and Storage Temperature Range TJ, TSTG -65 150 °C 2
Reverse Standoff Voltage VRWM 5.5 V 2
Channel Leakage Current IR 1 100 nA VR = 3V 2
Reverse breakdown voltage VBR 6 9 V IR = 1mA, from pin 4 to pin 1 2
Forward Voltage VF 0.8 V IF = 8mA 2
Dynamic Resistance RDYN 0.9 Ω IPP = 1A, tp = 8/20μs 2
I/O to GND Capacitance C(I/O-GND) 1 1.5 pF V(I/O-GND) = 0V, f = 1MHz 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin  Terminals: Matte Tin Finish annealed over Alloy 42 leadframe (Lead Free Plating). Solderable per MIL-STD-202, Method 208 1

CAD (land: KiCad; 3D: generated from the datasheet)

  • Symbol: DRTR5V0U2SR-7
  • Footprint: Package_TO_SOT_SMD:SOT-143
  • 3D model: SOT-143, generated on the KiCad land (body 1.3 x 2.9 mm, terminals on the pads, 0.9450000000000001 mm tall, datasheet A, midpoint of min and max). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
  • 3D model files: drtr5v0u2sr-7-etched.step / drtr5v0u2sr-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drtr5v0u2sr-7.step / drtr5v0u2sr-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (4 pp, sha256 14b5dca7d3d821eb, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).

Datasheet PDF