component
DRTR5V0U1SO-7
Public Made by Adomby adom
Diodes Incorporated ESD And Surge Protection (TVS/ESD), SOT-23. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownDRTR5V0U1SO-7
Diodes Incorporated · ESD And Surge Protection (TVS/ESD) · SOT-23
DRTR5V0U1SO-7 from Diodes Incorporated, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | ESD-protected I/O channel with 1.0pF typical (1.5pF max) capacitance to GND and 100nA max leakage at VR = 3V. |
| 2 | VCC | passive | Supply/reference pin of the TVS array with 5.5V reverse standoff voltage and 6.0V to 9.0V breakdown (IR = 1mA, pin 2 to pin 3). |
| 3 | GND | power_in | Ground reference pin for the TVS diode array, to which the I/O capacitance is measured. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-23 |
| Category | Circuit Protection |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reverse Standoff Voltage | VRWM | 5.5 | V | 2 | |||
| Channel Leakage Current | IR | 1 | 100 | nA | VR = 3V | 2 | |
| Reverse breakdown voltage | VBR | 6 | 9 | V | IR = 1mA, from pin 2 to pin 3 | 2 | |
| I/O to GND Capacitance | C(I/O-GND) | 1 | 1.5 | pF | V(I/O-GND) = 0V, f = 1MHz | 2 | |
| Peak Pulse Current | IPP | 5 | A | 8/20µs, Per Figure 3 | 2 | ||
| ESD Protection, Contact Discharge | VESD_Contact | -8 | 8 | kV | Standard IEC 61000-4-2 | 2 | |
| ESD Protection, Air Discharge | VESD_Air | -15 | 15 | kV | Standard IEC 61000-4-2 | 2 | |
| Power Dissipation | PD | 300 | mW | Note 5: device mounted on FR-4 PCB pad layout (2oz copper), Diodes suggested pad layout AP02001 | 2 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 417 | °C/W | Note 5: device mounted on FR-4 PCB pad layout (2oz copper), Diodes suggested pad layout AP02001 | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -65 | 150 | °C | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Terminals: Matte Tin Finish annealed over Alloy 42 leadframe (Lead Free Plating). Solderable per MIL-STD-202, Method 208 | 1 |
CAD (KiCad official)
- Symbol:
DRTR5V0U1SO-7 - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
drtr5v0u1so-7-etched.step/drtr5v0u1so-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drtr5v0u1so-7.step/drtr5v0u1so-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (4 pp, sha256
d910c768550bd52f, retrieved 2026-10-21, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).