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DP83TG720SWRHATQ1
Public Made by Adomby adom
Texas Instruments Ethernet ICs, VQFN-36(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDP83TG720SWRHATQ1
Texas Instruments · Ethernet ICs · VQFN-36(6x6)
DP83TG720SWRHATQ1 from Texas Instruments, in a VQFN-36(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MDC | input | Management data clock: synchronous clock for MDIO serial management input and output data. |
| 2 | INT_N | output | Active-low open-drain interrupt output with a weak internal pull-up; can be configured active-high via register 0x0011. |
| 3 | RESET_N | input | Active-low reset input with internal pull-up; hold low at least 10 µs to force reset, and strap pins are resampled on deassertion. |
| 4 | XO | output | Reference clock output used only with a crystal; leave floating when a CMOS oscillator drives XI. |
| 5 | XI | input | Reference clock input for a 25 MHz ±100 ppm crystal or CMOS oscillator (oscillator on XI only with XO floating). |
| 6 | LED_1/GPIO_1 | bidirectional | LED_1 shows link status, blinking on TX/RX activity; also the AUTO (autonomous/managed) strap pin with internal pull-down. |
| 7 | VSLEEP | power_in | 3.3 V sleep supply (2.97 to 3.63 V); connect to VDDA3P3 if the sleep function is not used. |
| 8 | WAKE | input | Active-high wake pulse input in the VSLEEP domain with internal pull-down that wakes the PHY from sleep; may be tied to VSLEEP if unused. |
| 9 | VDD1P0 | power_in | 1.0 V core supply (0.95 to 1.1 V); see decoupling network in power recommendations. |
| 10 | INH | output | Active-high PMOS open-drain output that drives VSLEEP rail level in all states except sleep, when it is released to an external pull-down (10 kΩ recommended). |
| 11 | VDDA3P3 | power_in | 3.3 V core supply (2.97 to 3.63 V); see decoupling network in power recommendations. |
| 12 | TRD_P | bidirectional | Positive differential transmit/receive MDI signal for IEEE 802.3bp 1000BASE-T1 operation. |
| 13 | TRD_M | bidirectional | Negative differential transmit/receive MDI signal for IEEE 802.3bp 1000BASE-T1 operation. |
| 14 | STRP_1 | input | Strap 1 pin (3-level, internal 6.3 kΩ pull-down) used to strap PHY_AD address bits. |
| 15 | RX_CTRL | bidirectional | RGMII receive control combining RX_DV (rising RX_CLK edge) and RX_ER (falling edge); a PHY_AD strap pin at reset and strap-only in SGMII mode. |
| 16 | CLKOUT/GPIO_2 | bidirectional | Clock output, 25 MHz buffered copy of XI by default; can be disabled by writing register 0x0453 = 0x0006. |
| 17 | DNC | unconnected | Do not connect; leave floating to avoid damage or entering a wrong PHY mode. |
| 18 | DNC | unconnected | Do not connect; leave floating to avoid damage or entering a wrong PHY mode. |
| 19 | DNC | unconnected | Do not connect; leave floating to avoid damage or entering a wrong PHY mode. |
| 20 | DNC | unconnected | Do not connect; leave floating to avoid damage or entering a wrong PHY mode. |
| 21 | VDD1P0 | power_in | 1.0 V core supply (0.95 to 1.1 V); see decoupling network in power recommendations. |
| 22 | VDDIO | power_in | IO supply of 1.8 V, 2.5 V or 3.3 V; see decoupling network in power recommendations. |
| 23 | RX_D3/RX_M | output | RGMII receive data bit 3 synchronous to RX_CLK, or SGMII differential data output RX_M to the MAC. |
| 24 | RX_D2/RX_P | output | RGMII receive data bit 2 synchronous to RX_CLK (also MAC[2] strap), or SGMII differential data output RX_P to the MAC. |
| 25 | RX_D1 | output | RGMII receive data bit 1 synchronous to RX_CLK; also MAC[1] interface-select strap. |
| 26 | RX_D0 | output | RGMII receive data bit 0 synchronous to RX_CLK; also MAC[0] interface-select strap. |
| 27 | RX_CLK | output | RGMII 125 MHz receive clock from PHY to MAC; unused in SGMII mode. |
| 28 | TX_CLK | input | RGMII 125 MHz transmit clock from MAC to PHY; unused in SGMII mode. |
| 29 | TX_CTRL | input | RGMII transmit control combining TX_EN (rising TX_CLK edge) and TX_ER (falling edge); unused in SGMII mode. |
| 30 | TX_D3 | input | RGMII transmit data bit 3 received from the MAC. |
| 31 | TX_D2 | input | RGMII transmit data bit 2 received from the MAC. |
| 32 | TX_D1/TX_P | input | RGMII transmit data bit 1 from the MAC, or SGMII differential data input TX_P. |
| 33 | TX_D0/TX_M | input | RGMII transmit data bit 0 from the MAC, or SGMII differential data input TX_M. |
| 34 | VDDIO | power_in | IO supply of 1.8 V, 2.5 V or 3.3 V; see decoupling network in power recommendations. |
| 35 | LED_0/GPIO_0 | bidirectional | LED_0 shows link status; also the MS strap (internal pull-down gives slave, external pull-up gives MDI master). |
| 36 | MDIO | bidirectional | Open-drain bidirectional management data signal requiring an external pull-up (2.2 kΩ recommended). |
| 37 | GND | power_in | Exposed die attach pad (DAP) ground; must be soldered to the PCB for thermal and mechanical performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-36(6x6) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 37 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDDA3P3 | VDDA3P3 | -0.5 | 4 | V | 10 | ||
| Supply voltage VDD1P0 | VDD1P0 | -0.5 | 1.4 | V | 10 | ||
| Supply voltage VDDIO (3.3V) | VDDIO | -0.5 | 4 | V | 3.3V | 10 | |
| Supply voltage VDDIO (2.5V) | VDDIO | -0.5 | 2.9 | V | 2.5V | 10 | |
| Supply voltage VDDIO (1.8V) | VDDIO | -0.5 | 2.2 | V | 1.8V | 10 | |
| Supply voltage VSLEEP | VSLEEP | -0.5 | 4 | V | 10 | ||
| MDI pins voltage | -0.5 | 4 | V | TRD_M, TRD_P | 10 | ||
| Junction temperature | TJ | 150 | °C | 10 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 10 | ||
| IO supply voltage, 1.8V operation | VDDIO | 1.62 | 1.8 | 1.98 | V | 10 | |
| IO supply voltage, 2.5V operation | VDDIO | 2.25 | 2.5 | 2.75 | V | 10 | |
| IO supply voltage, 3.3V operation | VDDIO | 2.97 | 3.3 | 3.63 | V | 10 | |
| Core supply voltage, 3.3V | VDDA3P3 | 2.97 | 3.3 | 3.63 | V | 10 | |
| Core supply voltage, 1.0V | VDD1P0 | 0.95 | 1 | 1.1 | V | 10 | |
| Sleep supply voltage, 3.3V | VSLEEP | 2.97 | 3.3 | 3.63 | V | 10 | |
| Ambient temperature | TA | -40 | 125 | °C | 11 | ||
| Junction-to-ambient thermal resistance | RθJA | 32.5 | °C/W | RHA (VQFN) 36 pin | 11 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 22.2 | °C/W | RHA (VQFN) 36 pin | 11 | ||
| Junction-to-board thermal resistance | RθJB | 13.3 | °C/W | RHA (VQFN) 36 pin | 11 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 3.2 | °C/W | RHA (VQFN) 36 pin | 11 | ||
| Input high current (MDIO) | IIH | -5 | 5 | µA | VIN = VCC, -40°C to 125°C | 12 | |
| Input high current (RGMII inputs, MDC) | IIH | -20 | 20 | µA | VIN = VCC, -40°C to 125°C | 12 | |
| Integrated pull-up resistance INT, RESET | Rpull-up | 6.5 | 9 | 12.5 | kΩ | INT, RESET | 12 |
| Integrated pull-down resistance STRP_1, RX_CTRL | Rpull-down | 4.725 | 6.3 | 7.875 | kΩ | STRP_1, RX_CTRL | 12 |
| Integrated pull-down resistance WAKE | Rpull-down | 35 | 50 | 62.5 | kΩ | WAKE | 12 |
| Sleep supply current | ISLEEP | 485 | 840 | µA | VSLEEP, sleep mode | 12 | |
| Operating temperature sensor accuracy (device to device) | -21.5 | 20 | ℃ | -40℃ to 125℃ | 14 | ||
| Oscillator frequency tolerance | -100 | 100 | ppm | Frequency tolerance and stability over temperature and aging | 15 |
CAD (KiCad official)
- Symbol:
DP83TG720SWRHATQ1 - Footprint:
Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm - 3D model: VQFN-36(6x6) (KiCad packages3D, STEP)
- 3D model files:
dp83tg720swrhatq1-etched.step/dp83tg720swrhatq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dp83tg720swrhatq1.step/dp83tg720swrhatq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (221 pp, sha256
da75069c2504ff7c, retrieved 2026-10-23, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).