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DP83TC814SRHARQ1

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Texas Instruments Ethernet ICs, VQFN-36(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232dp83tc814srharq1factory-2.0.0extractor-text

Verified DP83TC814SRHARQ1

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 37 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DP83TC814SRHARQ1 · VQFN-36(6x6) · 37 pins
  • ✓copper: 37 copper pads, none touching another net
  • ✓datasheet: all 37 pin names found in the 161-page datasheet
  • ✓distributor: lcsc C3225816, digikey 296-DP83TC814SRHARQ1TR-ND, mouser 595-DP83TC814SRHARQ1
  • ✓family: QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1m05qb22/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.158)
  • ✓pads: 37 pins = 37 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 37 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dp83tc814srharq1.kicad_sym✓ dp83tc814srharq1.kicad_mod✓ dp83tc814srharq1.step
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Ray Publish 0.1.0 9e2fb02 19h ago

DP83TC814SRHARQ1

Texas Instruments · Ethernet ICs · VQFN-36(6x6)

DP83TC814SRHARQ1 from Texas Instruments, in a VQFN-36(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MDC input Management data clock for MDIO serial management, asynchronous to the MAC clocks, maximum rate 20MHz with no minimum rate (VDDIO domain).
2 INT_N bidirectional Active-low open-drain interrupt output with weak internal pull-up that can also act as a power-down control input, polarity configurable via register 0x0011 (VDDIO domain).
3 RESET_N input Active-low reset input with internal pull-up; hold low for at least 1µs to reinitialize the PHY, and strap pins are resampled on deassertion (VDDIO domain).
4 XO output Crystal reference clock output used only with a crystal; must be left floating when a CMOS oscillator drives XI.
5 XI input 25MHz crystal or CMOS oscillator reference clock input (50MHz in RMII slave mode); use a 100Ω series resistor with a crystal.
6 LED_1/GPIO_1 bidirectional Link status LED (blinks on TX/RX activity) or GPIO that is also the AUTO strap pin with internal pull-down (VDDIO domain).
7 VDDA power_in 3.3V VDDA supply; 0.1µF ceramic decoupling capacitor recommended.
8 DNC unconnected Do not connect; leave floating.
9 NC unconnected No connect, floats on power-up; for DP83TC815 adaptation connect to pin 21.
10 DNC unconnected Do not connect; leave floating.
11 VDDA power_in 3.3V core supply; 0.47µF and 0.01µF ceramic decoupling capacitors recommended, optional ferrite bead.
12 TRD_P bidirectional Positive differential transmit/receive pin for IEEE 802.3bw 100BASE-T1 operation (VDDA domain, ±8kV HBM ESD).
13 TRD_M bidirectional Negative differential transmit/receive pin for IEEE 802.3bw 100BASE-T1 operation (VDDA domain, ±8kV HBM ESD).
14 RX_ER bidirectional Receive error output in MII/RMII modes, unused in RGMII/SGMII; also PHY_AD[1]/PHY_AD[3] 3-level strap with internal pull-down (VDDMAC domain).
15 RX_DV/CRS_DV/RX_CTRL bidirectional Receive data valid (MII), carrier sense/data valid (RMII) or RGMII receive control, unused in SGMII; also PHY_AD[0]/PHY_AD[2] 3-level strap with pull-down (VDDMAC domain).
16 CLKOUT/GPIO_2 bidirectional 25MHz reference clock output (50MHz in RMII slave mode), configurable as LED or GPIO, with AUTO strap function (VDDMAC domain).
17 GND_ESC passive Optional ground escape pin that may be tied to ground for PCB layout; not a substitute for the DAP ground, and may be left open.
18 GND_ESC passive Optional ground escape pin that may be tied to ground for PCB layout; not a substitute for the DAP ground, and may be left open.
19 DNC unconnected Do not connect; leave floating.
20 DNC unconnected Do not connect; leave floating.
21 NC unconnected No connect, floating; for DP83TC815 adaptation connect 2.2µF and 0.1µF ceramic capacitors from this pin to GND and connect pin 9 to it.
22 VDDMAC power_in Optional separate 1.8V, 2.5V or 3.3V supply for MAC interface pins; connect to VDDIO if no separate supply is needed, with 0.47µF and 0.01µF decoupling.
23 RX_D3/RX_M bidirectional Receive data bit 3 (MII/RGMII), SGMII differential output RX_M, or 50MHz RMII master clock output; CLKOUT_PIN strap with pull-down (VDDMAC domain).
24 RX_D2/RX_P bidirectional Receive data bit 2 (MII/RGMII) or SGMII differential output RX_P; MAC[2] strap with pull-down (VDDMAC domain).
25 RX_D1 bidirectional Receive data bit 1 synchronous to RX_CLK; MAC[1] interface-select strap with pull-down (VDDMAC domain).
26 RX_D0 bidirectional Receive data bit 0 synchronous to RX_CLK; MAC[0] interface-select strap with pull-down (VDDMAC domain).
27 RX_CLK bidirectional 25MHz receive clock in MII and RGMII modes, unused in RMII and SGMII, with internal pull-down (VDDMAC domain).
28 TX_CLK bidirectional 25MHz transmit clock output in MII mode or 25MHz clock input from the MAC in RGMII mode, unused in RMII and SGMII (VDDMAC domain).
29 TX_EN/TX_CTRL input Transmit enable (MII/RMII) or RGMII transmit control, unused in SGMII, with internal pull-down (VDDMAC domain).
30 TX_D3 input Transmit data bit 3 from the MAC in MII/RGMII modes, unused in RMII (VDDMAC domain).
31 TX_D2 input Transmit data bit 2 from the MAC in MII/RGMII modes, unused in RMII (VDDMAC domain).
32 TX_D1/TX_P input Transmit data bit 1 from the MAC or SGMII differential input TX_P (VDDMAC domain).
33 TX_D0/TX_M input Transmit data bit 0 from the MAC or SGMII differential input TX_M (VDDMAC domain).
34 VDDIO power_in 1.8V, 2.5V or 3.3V IO supply; ferrite bead, 0.47µF and 0.01µF ceramic decoupling recommended.
35 LED_0/GPIO_0 bidirectional Link status LED or GPIO that is also the MS master/slave strap pin with internal pull-down, defaulting to slave (VDDIO domain).
36 MDIO bidirectional Open-drain bidirectional management data line requiring a 2.2kΩ to 9kΩ pull-up to VDDIO (VDDIO domain).
37 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-36(6x6)
Category Communication Interface Chip/UART/485/232
Pins 37

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VDDA VDDA -0.3 4 V 14
Input voltage VDDIO/VDDMAC (3.3V) VDDIO/VDDMAC -0.3 4 V 3.3V 14
Input voltage VDDIO/VDDMAC (2.5V) VDDIO/VDDMAC -0.3 4 V 2.5V 14
Input voltage VDDIO/VDDMAC (1.8V) VDDIO/VDDMAC -0.3 4 V 1.8V 14
Pin MDI voltage -0.3 4 V Pin MDI 14
MAC interface pin voltage -0.3 V Pin MAC interface; max printed as VDDMAC + 0.3 V 14
MDIO, MDC, GPIO, XI, XO, INT, RESET, CLKOUT pin voltage -0.3 V max printed as VDDIO + 0.3 V 14
DC output voltage -0.3 4 V All pins 14
Junction temperature TJ 150 °C 14
Storage temperature Tstg -65 150 °C 14
HBM ESD, all pins V(ESD) -2000 2000 V HBM per AEC Q100-002, all pins 14
HBM ESD, TRD_N/TRD_P V(ESD) -8000 8000 V HBM per AEC Q100-002, TRD_N, TRD_P pins 14
CDM ESD V(ESD) -750 750 V CDM per AEC Q100-011, corner pins and other pins 14
IEC 61000-4-2 contact discharge V(ESD) -8000 8000 V TRD_N, TRD_P pins 14
IO supply voltage, 1.8V operation VDDIO/VDDMAC 1.62 1.8 1.98 V 1.8V operation 14
IO supply voltage, 2.5V operation VDDIO/VDDMAC 2.25 2.5 2.75 V 2.5V operation 14
IO supply voltage, 3.3V operation VDDIO/VDDMAC 2.97 3.3 3.63 V 3.3V operation 14
Core supply voltage VDDA 2.97 3.3 3.63 V 3.3V 14
Ambient temperature TA -40 125 °C 14
Junction-to-ambient thermal resistance RθJA 36.7 °C/W RHA (VQFN) 36 pins 15
Junction-to-case (top) thermal resistance RθJC(top) 27 °C/W RHA (VQFN) 36 pins 15
Junction-to-board thermal resistance RθJB 17.5 °C/W RHA (VQFN) 36 pins 15
Junction-to-top characterization parameter ΨJT 0.7 °C/W RHA (VQFN) 36 pins 15
Junction-to-board characterization parameter ΨJB 17.5 °C/W RHA (VQFN) 36 pins 15
Junction-to-case (bottom) thermal resistance RθJC(bot) 6.7 °C/W RHA (VQFN) 36 pins 15
High-level input voltage VIH 2 V VDDIO = 3.3V ±10% 15
Low-level input voltage VIL 0.8 V VDDIO = 3.3V ±10% 16
High-level output voltage VOH 2.4 V IOH = -2mA, VDDIO = 3.3V ±10% 16
Low-level output voltage VOL 0.4 V IOL = 2mA, VDDIO = 3.3V ±10% 16
High-level input voltage VIH 1.7 V VDDIO = 2.5V ±10% 16
Low-level input voltage VIL 0.7 V VDDIO = 2.5V ±10% 16
High-level output voltage VOH 2 V IOH = -2mA, VDDIO = 2.5V ±10% 16
Low-level output voltage VOL 0.45 V IOL = 2mA, VDDIO = 1.8V ±10% 16
Input high current IIH -10 10 µA TA = -40℃ to 125℃, VIN=VDDIO, all pins except XI 16
Input low current IIL -10 10 µA TA = -40℃ to 125℃, VIN=GND, all pins except XI 16
Tri-state output high current Iozh -10 10 µA TA = -40℃ to 125℃, VIN = VDDIO, all pins except RX_CTRL and RX_ER 16
Tri-state output high current Iozh -52 52 µA TA = -40℃ to 125℃, VIN = VDDIO, RX_CTRL and RX_ER 16
Tri-state output low current Iozl -10 10 µA TA = -40℃ to 125℃, VOUT = GND 16
Internal pull-down resistor Rpulldn 6.2 8.4 10.7 kΩ RX_D[3:0], RX_CLK, LED_0, LED_1 16
Internal pull-down resistor Rpulldn 4.725 5.8 7.2 kΩ RX_CTRL, RX_ER 16
Internal pull-up resistor Rpullup 6.3 9 11.2 kΩ INT, RESET 16
Integrated MAC series termination resistor Rseries 35 50 65 Ω RX_D[3:0], RX_ER, RX_DV, RX_CLK 16
I(3V3) supply current, MII I(3V3) 57 63 mA MII -40°C to 125°C 16
I(3V3) supply current, RMII I(3V3) 57 63 mA RMII -40°C to 125°C 16
I(3V3) supply current, RGMII I(3V3) 57 63 mA RGMII -40°C to 125°C 16
I(3V3) supply current, SGMII I(3V3) 81 95 mA SGMII -40°C to 125°C 16
I(VDDIO=3.3V) supply current, MII I(VDDIO=3.3V) 19 24 mA MII, -40℃ to 125℃, VDDIO = VDDMAC 16
I(VDDIO=3.3V) supply current, RGMII I(VDDIO=3.3V) 13 21 mA RGMII, -40℃ to 125℃, VDDIO = VDDMAC 17
I(VDDIO=3.3V) supply current, SGMII I(VDDIO=3.3V) 7 12 mA SGMII, -40℃ to 125℃, VDDIO = VDDMAC 17
I(VDDA3V3) IEEE power-down I(VDDA3V3) 8 22 mA IEEE power down, -40℃ to 125℃, all interfaces 17
I(VDDA3V3) reset I(VDDA3V3) 9 23 mA Reset, -40℃ to 125℃, all interfaces 17
I(VDDA3V3) standby, MII I(VDDA3V3) 15 33 mA Standby, -40°C to 125°C, MII 17
SGMII output clock duty cycle 48 52 % SO_P and SO_N, AC coupled, 0101010101 pattern 18
SGMII output differential voltage 150 400 mV SO_P and SO_N, AC coupled 18
SGMII receiver differential input impedance (DC) RIN-DIFF 80 120 Ω 18
VDDA sensor accuracy (single device, voltage and temperature variation) -120 120 mV -40°C to +125°C 18
VDDIO/VDDMAC sensor accuracy (single device, voltage and temperature variation) -144 144 mV -40°C to +125°C 18
Power supply ramp time, all supplies T5.1 0.2 8 ms 19

CAD (KiCad official)

  • Symbol: DP83TC814SRHARQ1
  • Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
  • 3D model: VQFN-36(6x6) (KiCad packages3D, STEP)
  • 3D model files: dp83tc814srharq1-etched.step / dp83tc814srharq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83tc814srharq1.step / dp83tc814srharq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (161 pp, sha256 d1fe2a72e0f7d7e6, retrieved 2026-10-31, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF