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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83TC813SRHFRQ1

Texas Instruments · Ethernet Transceivers · VQFN-28(4x5)

DP83TC813SRHFRQ1 from Texas Instruments, in a VQFN-28(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TX_CLK	bidirectional	MII mode: 25 MHz output (50 Ω driver) with constant phase referenced to the reference clock; RGMII mode: 25 MHz clock input from the MAC that must be provided; not used in RMII and SGMII modes.
2	TX_EN/TX_CTRL	input	Transmit enable input: in MII it precedes the TX_CLK rising edge and indicates valid TX_D[3:0] data; in RGMII it is the transmit control input combining TX_EN and TX_ER; not used in SGMII mode.
3	TX_D3	input	Transmit data nibble bit 3 from the MAC, latched before the TX_CLK rising edge in MII/RGMII mode; not used in RMII slave mode.
4	TX_D2	input	Transmit data nibble bit 2 from the MAC, latched before the TX_CLK rising edge in MII/RGMII mode; not used in RMII slave mode.
5	TX_D1/TX_P	input	Transmit data bit 1 in MII/RGMII/RMII modes; in SGMII mode this pin is the TX_P differential data input receiving data from the MAC.
6	TX_D0/TX_M	input	Transmit data bit 0 in MII/RGMII/RMII modes; in SGMII mode this pin is the TX_M differential data input receiving data from the MAC.
7	VDDIO	power_in	I/O supply selectable at 1.8 V, 2.5 V or 3.3 V (recommended 1.62-1.98 V, 2.25-2.75 V or 2.97-3.63 V); decouple with ferrite bead, 0.47 µF and 0.01 µF capacitors.
8	MDIO	bidirectional	Open-drain management data input/output for the SMI bus; requires a pull-up to VDDIO, with 2.2 kΩ to 9 kΩ recommended.
9	MDC	input	Management data clock input that synchronizes MDIO transfers; MDC frequency range is 2.5 MHz to 20 MHz per the timing table and may be asynchronous to the MAC clocks.
10	INT_N	bidirectional	Active-low open-drain interrupt output with weak internal pull-up (9 kΩ typ.); can alternatively be configured as a power-down input.
11	RESET_N	input	Active-low reset input with internal pull-up (9 kΩ typ.) that reinitializes the PHY; must be held low for at least 1 µs to force a reset, and bootstrap pins are resampled on release.
12	XO	output	Crystal oscillator output used only with a 25 MHz crystal; must be left unconnected when XI is driven by a CMOS-level oscillator.
13	XI	input	Reference clock input: 25 MHz crystal or oscillator (50 MHz CMOS oscillator in RMII slave mode); a 100 Ω series resistor is required in series with XI when a crystal is used.
14	CLKOUT/LED_1	bidirectional	Multiplexed pin: 25 MHz reference clock output (50 MHz in RMII slave mode) by default, or LED_1/GPIO output when configured by register.
15	VSLEEP	power_in	TC-10 sleep supply at 3.3 V (recommended 2.97-3.63 V); a 0.1 µF ceramic decoupling capacitor is recommended.
16	WAKE	bidirectional	High-level input that wakes the PHY from TC-10 sleep and can be tied directly to VSLEEP; a 10 kΩ external pull-down is recommended to prevent accidental wake-up.
17	INH	bidirectional	Active-high open-drain output that is high-impedance in TC-10 sleep and high in all other states; an external 2 kΩ-10 kΩ pull-down is required when implementing TC-10.
18	VDDA	power_in	Core supply at 3.3 V (recommended 2.97-3.63 V); decouple with 0.47 µF and 0.01 µF ceramic capacitors, optional ferrite bead.
19	TRD_P	bidirectional	Positive leg of the 100BASE-T1 differential media interface (IEEE 802.3bw), connected through the common-mode choke and DC-blocking/ESD network.
20	TRD_M	bidirectional	Negative leg of the 100BASE-T1 differential media interface (IEEE 802.3bw), connected through the common-mode choke and DC-blocking/ESD network.
21	RX_ER	output	Receive error output that flags a receive error symbol in MII and RMII modes; not used in RGMII and SGMII modes.
22	RX_DV/CRS_DV/RX_CTRL	output	Mode-dependent receive output: RX_DV (valid data) in MII, CRS_DV (carrier sense/data valid) in RMII (default, register 0x0551 = 0x0010), or RX_CTRL in RGMII; not used in SGMII mode; has internal pull-down (6 kΩ typ.) as strap.
23	VDDMAC	power_in	Optional separate MAC-interface supply at 1.8 V, 2.5 V or 3.3 V; must be connected to VDDIO when a separate MAC supply is not needed.
24	RX_D3/RX_M	output	Receive data bit 3 in MII/RGMII; in RMII master mode it outputs a 50 MHz clock that must be fed to the MAC; in SGMII mode it is the RX_M differential data output to the MAC.
25	RX_D2/RX_P	output	Receive data bit 2 in MII/RGMII; not used in RMII slave mode; in SGMII mode it is the RX_P differential data output to the MAC.
26	RX_D1	output	Receive data bit 1, presented synchronously to the RX_CLK rising edge; used as RX_D[1:0] in RMII mode.
27	RX_D0	output	Receive data bit 0, presented synchronously to the RX_CLK rising edge; used as RX_D[1:0] in RMII mode.
28	RX_CLK	output	Receive clock providing a 25 MHz reference clock in MII and RGMII modes; not used in RMII and SGMII modes.
29	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-28(4x5)
Category	Interface
Pins	29

CAD (KiCad official)

Symbol: DP83TC813SRHFRQ1
Footprint: Package_DFN_QFN:QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
3D model: VQFN-28(4x5) (KiCad packages3D, STEP)
3D model files: dp83tc813srhfrq1-etched.step / dp83tc813srhfrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83tc813srhfrq1.step / dp83tc813srhfrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (176 pp, sha256 6192afa4f2470823, retrieved 2026-10-10, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF