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DP83TC811SWRNDRQ1
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Texas Instruments Ethernet Transceivers, UQFN-36-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+73@@ -0,0 +1,73 @@+# DP83TC811SWRNDRQ1++**Texas Instruments** · Ethernet Transceivers · UQFN-36-EP(6x6)++DP83TC811SWRNDRQ1 from Texas Instruments, in a UQFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | MDC | input | Management Data Clock, synchronous to MDIO; maximum clock rate 25 MHz with no minimum clock rate, and may be asynchronous to the MAC clocks. |+| 2 | INT_N | output | Active-LOW interrupt output with a weak internal pullup, asserted LOW on an interrupt condition and cleared through register access; can be configured as active-HIGH via INT_TEST register. |+| 3 | RESET_N | input | Active-LOW reset input with internal pullup; asserting LOW for at least 1 µs forces a device reset, and all bootstrap pins are resampled on deassertion. |+| 4 | XO | output | Crystal-only reference clock output; leave floating when a CMOS-level oscillator drives XI. |+| 5 | XI | input | Reference clock input for a 25-MHz crystal or CMOS oscillator (MII/RGMII/SGMII), or 50-MHz oscillator in RMII Slave mode or 25-MHz in RMII Master mode; this is a fail-safe pin that prevents back-driving when the PHY is unpowered. |+| 6 | LED_1 / GPIO_1 | bidirectional | LED_1 indicates link status and blinks for TX/RX activity; the pin is also a strap pin that must only be set for bootstrap MODE 1 or MODE 4. |+| 7 | EN | input | Active-HIGH enable with internal pulldown; pulling it LOW disables the device and powers down all internal blocks, and it can be tied directly to VDDIO to enable the device. |+| 8 | WAKE | input | Active-HIGH input with internal pulldown that wakes the PHY from SLEEP; asserting it HIGH at power-up prevents the PHY from entering SLEEP, and it can be tied directly to VDDIO. |+| 9 | DNC | unconnected | Do not connect; leave floating. |+| 10 | INH | output | Active-HIGH output asserted HIGH when the PHY is in SLEEP or DISABLED and LOW in all other states. |+| 11 | VDDA | power_in | Core supply at 3.3 V; use 10-nF, 100-nF, 1-µF and 10-µF ceramic decoupling capacitors, with an optional ferrite bead. |+| 12 | TRD_P | bidirectional | Positive leg of the differential transmit/receive pair for 100BASE-T1 operation (IEEE 802.3bw compliant); rated for ±8-kV IEC61000-4-2 contact discharge per the ESD classification. |+| 13 | TRD_M | bidirectional | Negative leg of the differential transmit/receive pair for 100BASE-T1 operation (IEEE 802.3bw compliant); rated for ±8-kV IEC61000-4-2 contact discharge per the ESD classification. |+| 14 | RX_ER | bidirectional | Receive error output with internal pulldown in MII and RMII modes, asserted on a receive error symbol; unused in RGMII and SGMII modes and sampled as a bootstrap pin at reset. |+| 15 | RX_DV / CRS_DV / RX_CTRL | bidirectional | Receive data valid in MII, carrier sense/data valid in RMII, and RGMII receive control output with internal pulldown; sampled as a bootstrap pin at reset. |+| 16 | CLKOUT / GPIO_2 | bidirectional | Configurable I/O that outputs a 25-MHz reference clock as CLKOUT or serves as GPIO_2 through register configuration. |+| 17 | TCK | input | JTAG test clock with internal pullup, the primary clock for all test logic; may be left unconnected if not used. |+| 18 | TDO | output | JTAG test data output on which test results are scanned out; may be left unconnected if not used. |+| 19 | TMS | input | JTAG test mode select with internal pullup that sequences the 16-state Tap Controller; TI recommends three clock cycles with TMS HIGH to reset JTAG, and it may be left unconnected if not used. |+| 20 | TDI | input | JTAG test data input with internal pullup into which test data is scanned; may be left unconnected if not used. |+| 21 | DNC | unconnected | Do not connect; leave floating. |+| 22 | VDDIO | power_in | I/O supply configurable at 1.8 V, 2.5 V or 3.3 V; use 10-nF, 100-nF, 1-µF and 10-µF ceramic decoupling capacitors, with an optional ferrite bead. |+| 23 | RX_D3 / RX_M | bidirectional | RX_D3 is an MII/RGMII receive data bit (not used in RMII except as the 50-MHz RMII reference output in RMII Master mode), and RX_M is the negative SGMII differential data output; strap pin, must be strapped to MODE 1. |+| 24 | RX_D2 / RX_P | bidirectional | RX_D2 is an MII/RGMII receive data bit (not used in RMII), and RX_P is the positive SGMII differential data output synchronous to the SGMII clock; strap pin with internal pulldown. |+| 25 | RX_D1 / RXCLK_M | bidirectional | RX_D1 is a receive data bit used in MII, RGMII and RMII modes, and RXCLK_M is the negative SGMII 625-MHz differential clock output in 6-wire SGMII mode; strap pin with internal pulldown. |+| 26 | RX_D0 / RXCLK_P | bidirectional | RX_D0 is a receive data bit used in MII, RGMII and RMII modes, and RXCLK_P is the positive SGMII 625-MHz differential clock output in 6-wire SGMII mode; strap pin with internal pulldown. |+| 27 | RX_CLK | output | Receive clock providing a 25-MHz reference in MII and RGMII modes; unused in RMII and SGMII modes. |+| 28 | TX_CLK | bidirectional | In MII mode a 25-MHz output with constant phase to the reference clock; in RGMII mode a 25-MHz input from the MAC, with internal pulldown; unused in RMII and SGMII modes. |+| 29 | TX_EN / TX_CTRL | input | Transmit enable input with internal pulldown, presented before the rising edge of the transmit clock in MII and RMII, and a combined transmit control signal in RGMII; unused in SGMII mode. |+| 30 | TX_D3 | input | Transmit data bit with internal pulldown, received from the MAC before the rising edge of TX_CLK in MII and RGMII; not used in RMII mode. |+| 31 | TX_D2 | input | Transmit data bit with internal pulldown, received from the MAC before the rising edge of TX_CLK in MII and RGMII; not used in RMII mode. |+| 32 | TX_D1 / TX_P | input | Transmit data bit with internal pulldown used in MII, RGMII and RMII modes, and TX_P is the positive SGMII differential data input from the MAC. |+| 33 | TX_D0 / TX_M | input | Transmit data bit with internal pulldown used in MII, RGMII and RMII modes, and TX_M is the negative SGMII differential data input from the MAC. |+| 34 | TX_ER | input | Transmit error input with internal pulldown that indicates a transmit error symbol in MII mode, received before the rising edge of TX_CLK; unused in RMII, RGMII and SGMII modes. |+| 35 | LED_0 / GPIO_0 | bidirectional | LED_0 indicates link status and is also a strap pin with internal pulldown that must only be set for bootstrap MODE 1 or MODE 4. |+| 36 | MDIO | bidirectional | Open-drain management data input/output that requires a pullup resistor, recommended between 2.2 kΩ and 9 kΩ. |+| 37 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | UQFN-36-EP(6x6) |+| Category | Interface |+| Pins | 37 |++## CAD (KiCad official)++- Symbol: `DP83TC811SWRNDRQ1`+- Footprint: `Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm`+- 3D model: UQFN-36-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `dp83tc811swrndrq1-etched.step` / `dp83tc811swrndrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83tc811swrndrq1.step` / `dp83tc811swrndrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83tc811s-q1) (136 pp, sha256 `178301b957815077`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dp83tc811swrndrq1-datasheet.pdf)
page.jsonadded+377@@ -0,0 +1,377 @@+{+ "slug": "dp83tc811swrndrq1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Ethernet Transceivers, UQFN-36-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "dp83tc811swrndrq1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dp83tc811swrndrq1.kicad_sym",+ "dp83tc811swrndrq1.kicad_mod",+ "dp83tc811swrndrq1.glb",+ "dp83tc811swrndrq1.step",+ "dp83tc811swrndrq1.lbr",+ "docs/hero.png",+ "docs/dp83tc811swrndrq1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dp83tc811swrndrq1-hero.glb",+ "dp83tc811swrndrq1-hero.overlay.json"+ ],+ "component": {+ "mpn": "DP83TC811SWRNDRQ1",+ "manufacturer": "Texas Instruments",+ "package": "UQFN-36-EP(6x6)",+ "pin_count": 37,+ "category": "Interface",+ "subcategory": "Ethernet Transceivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dp83tc811s-q1",+ "parts": {+ "symbol": "dp83tc811swrndrq1.kicad_sym",+ "footprint": "dp83tc811swrndrq1.kicad_mod",+ "model_3d": "dp83tc811swrndrq1-hero.glb",+ "model_3d_plain": "dp83tc811swrndrq1.glb",+ "model_3d_step": "dp83tc811swrndrq1-etched.step",+ "model_3d_step_plain": "dp83tc811swrndrq1.step",+ "lbr": "dp83tc811swrndrq1.lbr"+ },+ "distributor_links": {+ "lcsc": "C1848117",+ "digikey": "296-DP83TC811SWRNDRQ1TR-ND",+ "mouser": "595-DP83TC811SWRNDRQ"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T01:59:15Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-DP83TC811SWRNDRQ1TR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DP83TC811SWRNDRQ",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "MDC",+ "type": "input",+ "description": "Management Data Clock, synchronous to MDIO; maximum clock rate 25 MHz with no minimum clock rate, and may be asynchronous to the MAC clocks."+ },+ {+ "number": "2",+ "name": "INT_N",+ "type": "output",+ "description": "Active-LOW interrupt output with a weak internal pullup, asserted LOW on an interrupt condition and cleared through register access; can be configured as active-HIGH via INT_TEST register."+ },+ {+ "number": "3",+ "name": "RESET_N",+ "type": "input",+ "description": "Active-LOW reset input with internal pullup; asserting LOW for at least 1 µs forces a device reset, and all bootstrap pins are resampled on deassertion."+ },+ {+ "number": "4",+ "name": "XO",+ "type": "output",+ "description": "Crystal-only reference clock output; leave floating when a CMOS-level oscillator drives XI."+ },+ {+ "number": "5",+ "name": "XI",+ "type": "input",+ "description": "Reference clock input for a 25-MHz crystal or CMOS oscillator (MII/RGMII/SGMII), or 50-MHz oscillator in RMII Slave mode or 25-MHz in RMII Master mode; this is a fail-safe pin that prevents back-driving when the PHY is unpowered."+ },+ {+ "number": "6",+ "name": "LED_1 / GPIO_1",+ "type": "bidirectional",+ "description": "LED_1 indicates link status and blinks for TX/RX activity; the pin is also a strap pin that must only be set for bootstrap MODE 1 or MODE 4."+ },+ {+ "number": "7",+ "name": "EN",+ "type": "input",+ "description": "Active-HIGH enable with internal pulldown; pulling it LOW disables the device and powers down all internal blocks, and it can be tied directly to VDDIO to enable the device."+ },+ {+ "number": "8",+ "name": "WAKE",+ "type": "input",+ "description": "Active-HIGH input with internal pulldown that wakes the PHY from SLEEP; asserting it HIGH at power-up prevents the PHY from entering SLEEP, and it can be tied directly to VDDIO."+ },+ {+ "number": "9",+ "name": "DNC",+ "type": "unconnected",+ "description": "Do not connect; leave floating."+ },+ {+ "number": "10",+ "name": "INH",+ "type": "output",+ "description": "Active-HIGH output asserted HIGH when the PHY is in SLEEP or DISABLED and LOW in all other states."+ },+ {+ "number": "11",+ "name": "VDDA",+ "type": "power_in",+ "description": "Core supply at 3.3 V; use 10-nF, 100-nF, 1-µF and 10-µF ceramic decoupling capacitors, with an optional ferrite bead."+ },+ {+ "number": "12",+ "name": "TRD_P",+ "type": "bidirectional",+ "description": "Positive leg of the differential transmit/receive pair for 100BASE-T1 operation (IEEE 802.3bw compliant); rated for ±8-kV IEC61000-4-2 contact discharge per the ESD classification."+ },+ {+ "number": "13",+ "name": "TRD_M",+ "type": "bidirectional",+ "description": "Negative leg of the differential transmit/receive pair for 100BASE-T1 operation (IEEE 802.3bw compliant); rated for ±8-kV IEC61000-4-2 contact discharge per the ESD classification."+ },+ {+ "number": "14",+ "name": "RX_ER",+ "type": "bidirectional",+ "description": "Receive error output with internal pulldown in MII and RMII modes, asserted on a receive error symbol; unused in RGMII and SGMII modes and sampled as a bootstrap pin at reset."+ },+ {+ "number": "15",+ "name": "RX_DV / CRS_DV / RX_CTRL",+ "type": "bidirectional",+ "description": "Receive data valid in MII, carrier sense/data valid in RMII, and RGMII receive control output with internal pulldown; sampled as a bootstrap pin at reset."+ },+ {+ "number": "16",+ "name": "CLKOUT / GPIO_2",+ "type": "bidirectional",+ "description": "Configurable I/O that outputs a 25-MHz reference clock as CLKOUT or serves as GPIO_2 through register configuration."+ },+ {+ "number": "17",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock with internal pullup, the primary clock for all test logic; may be left unconnected if not used."+ },+ {+ "number": "18",+ "name": "TDO",+ "type": "output",+ "description": "JTAG test data output on which test results are scanned out; may be left unconnected if not used."+ },+ {+ "number": "19",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test mode select with internal pullup that sequences the 16-state Tap Controller; TI recommends three clock cycles with TMS HIGH to reset JTAG, and it may be left unconnected if not used."+ },+ {+ "number": "20",+ "name": "TDI",+ "type": "input",+ "description": "JTAG test data input with internal pullup into which test data is scanned; may be left unconnected if not used."+ },+ {+ "number": "21",+ "name": "DNC",+ "type": "unconnected",+ "description": "Do not connect; leave floating."+ },+ {+ "number": "22",+ "name": "VDDIO",+ "type": "power_in",+ "description": "I/O supply configurable at 1.8 V, 2.5 V or 3.3 V; use 10-nF, 100-nF, 1-µF and 10-µF ceramic decoupling capacitors, with an optional ferrite bead."+ },+ {+ "number": "23",+ "name": "RX_D3 / RX_M",+ "type": "bidirectional",+ "description": "RX_D3 is an MII/RGMII receive data bit (not used in RMII except as the 50-MHz RMII reference output in RMII Master mode), and RX_M is the negative SGMII differential data output; strap pin, must be strapped to MODE 1."+ },+ {+ "number": "24",+ "name": "RX_D2 / RX_P",+ "type": "bidirectional",+ "description": "RX_D2 is an MII/RGMII receive data bit (not used in RMII), and RX_P is the positive SGMII differential data output synchronous to the SGMII clock; strap pin with internal pulldown."+ },+ {+ "number": "25",+ "name": "RX_D1 / RXCLK_M",+ "type": "bidirectional",+ "description": "RX_D1 is a receive data bit used in MII, RGMII and RMII modes, and RXCLK_M is the negative SGMII 625-MHz differential clock output in 6-wire SGMII mode; strap pin with internal pulldown."+ },+ {+ "number": "26",+ "name": "RX_D0 / RXCLK_P",+ "type": "bidirectional",+ "description": "RX_D0 is a receive data bit used in MII, RGMII and RMII modes, and RXCLK_P is the positive SGMII 625-MHz differential clock output in 6-wire SGMII mode; strap pin with internal pulldown."+ },+ {+ "number": "27",+ "name": "RX_CLK",+ "type": "output",+ "description": "Receive clock providing a 25-MHz reference in MII and RGMII modes; unused in RMII and SGMII modes."+ },+ {+ "number": "28",+ "name": "TX_CLK",+ "type": "bidirectional",+ "description": "In MII mode a 25-MHz output with constant phase to the reference clock; in RGMII mode a 25-MHz input from the MAC, with internal pulldown; unused in RMII and SGMII modes."+ },+ {+ "number": "29",+ "name": "TX_EN / TX_CTRL",+ "type": "input",+ "description": "Transmit enable input with internal pulldown, presented before the rising edge of the transmit clock in MII and RMII, and a combined transmit control signal in RGMII; unused in SGMII mode."+ },+ {+ "number": "30",+ "name": "TX_D3",+ "type": "input",+ "description": "Transmit data bit with internal pulldown, received from the MAC before the rising edge of TX_CLK in MII and RGMII; not used in RMII mode."+ },+ {+ "number": "31",+ "name": "TX_D2",+ "type": "input",+ "description": "Transmit data bit with internal pulldown, received from the MAC before the rising edge of TX_CLK in MII and RGMII; not used in RMII mode."+ },+ {+ "number": "32",+ "name": "TX_D1 / TX_P",+ "type": "input",+ "description": "Transmit data bit with internal pulldown used in MII, RGMII and RMII modes, and TX_P is the positive SGMII differential data input from the MAC."+ },+ {+ "number": "33",+ "name": "TX_D0 / TX_M",+ "type": "input",+ "description": "Transmit data bit with internal pulldown used in MII, RGMII and RMII modes, and TX_M is the negative SGMII differential data input from the MAC."+ },+ {+ "number": "34",+ "name": "TX_ER",+ "type": "input",+ "description": "Transmit error input with internal pulldown that indicates a transmit error symbol in MII mode, received before the rising edge of TX_CLK; unused in RMII, RGMII and SGMII modes."+ },+ {+ "number": "35",+ "name": "LED_0 / GPIO_0",+ "type": "bidirectional",+ "description": "LED_0 indicates link status and is also a strap pin with internal pulldown that must only be set for bootstrap MODE 1 or MODE 4."+ },+ {+ "number": "36",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Open-drain management data input/output that requires a pullup resistor, recommended between 2.2 kΩ and 9 kΩ."+ },+ {+ "number": "37",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package name mismatch: the requested package is 'UQFN-36-EP(6x6)', but the datasheet and the MPN's p; The top-view pin map on page 3 is garbled in the text extraction, so pin numbers were taken from the; The exposed die pad (DAP) is a ground pad with no printed pin number; it is listed as 'DAP' rather t",+ "exposed pad 37 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint",+ "1/37 pins cited to the wrong page (name found elsewhere): ['2:INT_N@p6']"+ ],+ "pages_sent": 15,+ "cost_usd": 0.11,+ "at": "2026-10-08T01:58:55"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dp83tc811s-q1",+ "pages": 136,+ "sha256": "178301b957815077",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 37,+ "described": 37,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dp83tc811swrndrq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "6212c4fd2463ccb7c6ae2c35f5e24c80884153fcaeaf8e86549c0e49087bc8bb",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dp83tc811swrndrq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b7394fe0bd1956e037ef5ec92a2b3e2a3c4add1d7d5840eae171b513bd3e9940",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}