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DP83867ISRGZT

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Texas Instruments Ethernet Transceivers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DP83867ISRGZT

Texas Instruments · Ethernet Transceivers · VQFN-48-EP(7x7)

DP83867ISRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TD_P_A passive Differential transmit and receive signal pair A positive side for 10BASE-Te, 100BASE-TX, and 1000BASE-T.
2 TD_M_A passive Differential transmit and receive signal pair A negative side for 10BASE-Te, 100BASE-TX, and 1000BASE-T.
3 VDDA2P5 power_in 2.5V analog power supply with ±5% tolerance; requires 1µF and 0.1µF bypass capacitors to ground.
4 TD_P_B passive Differential transmit and receive signal pair B positive side for 10BASE-Te, 100BASE-TX, and 1000BASE-T.
5 TD_M_B passive Differential transmit and receive signal pair B negative side for 10BASE-Te, 100BASE-TX, and 1000BASE-T.
6 VDD1P0 power_in 1V analog power supply with +15.5%, -5% tolerance; requires 1µF and 0.1µF bypass capacitors to ground.
7 TD_P_C passive Differential transmit and receive signal pair C positive side for 1000BASE-T operation only.
8 TD_M_C passive Differential transmit and receive signal pair C negative side for 1000BASE-T operation only.
9 VDDA2P5 power_in 2.5V analog power supply with ±5% tolerance; requires 1µF and 0.1µF bypass capacitors to ground.
10 TD_P_D passive Differential transmit and receive signal pair D positive side for 1000BASE-T operation only.
11 TD_M_D passive Differential transmit and receive signal pair D negative side for 1000BASE-T operation only.
12 RBIAS passive Bias resistor connection point requiring external 11kΩ ±1% resistor to ground for MDI termination.
13 VDDA1P8 power_in 1.8V analog power supply with ±5% tolerance; internal generation by default or accept external 1.8V with 1µF and 0.1µF bypass capacitors.
14 XO output Crystal oscillator output connection for 25MHz crystal; leave floating when using external clock source.
15 XI input 25MHz crystal or oscillator input accepting 50ppm accuracy with 1.5V to 1.9V peak input voltage.
16 MDC input Management data clock input for serial management interface with maximum frequency of 25MHz.
17 MDIO bidirectional Management data input/output for IEEE 802.3 serial management interface requiring 1.5kΩ external pull-up resistor.
18 CLK_OUT output Programmable clock output selectable as 25MHz or 125MHz synchronized to specified clock source.
19 VDDIO power_in I/O power supply selectable as 3.3V, 2.5V, or 1.8V with ±5% tolerance; requires 1µF and 0.1µF bypass capacitors.
20 JTAG_CLK input IEEE 1149.1 JTAG test clock input with maximum frequency of 2.5MHz and internal pull-up resistor.
21 JTAG_TDO output IEEE 1149.1 JTAG test data output for serial scanning of test results from device.
22 JTAG_TMS input IEEE 1149.1 JTAG test mode select input with internal pull-up; hold high with 3 clock cycles to reset TAP controller.
23 JTAG_TDI input IEEE 1149.1 JTAG test data input with internal pull-up for serial scanning of test data into device.
24 VDD1P0 power_in 1V analog power supply with +15.5%, -5% tolerance; requires 1µF and 0.1µF bypass capacitors to ground.
25 TX_D3 input RGMII transmit data bit 3 synchronized to GTX_CLK for MAC-to-PHY transmission in RGMII mode.
26 TX_D2 input RGMII transmit data bit 2 synchronized to GTX_CLK for MAC-to-PHY transmission in RGMII mode.
27 SGMII_SIP input SGMII differential transmit data positive input (also TX_D1 in RGMII mode); AC coupled via 0.1µF capacitor in SGMII mode.
28 SGMII_SIN input SGMII differential transmit data negative input (also TX_D0 in RGMII mode); AC coupled via 0.1µF capacitor in SGMII mode.
29 GTX_CLK input RGMII transmit clock input from MAC with nominal frequency 125MHz for gigabit mode.
30 VDDIO power_in I/O power supply selectable as 3.3V, 2.5V, or 1.8V with ±5% tolerance; requires 1µF and 0.1µF bypass capacitors.
31 VDD1P0 power_in 1V analog power supply with +15.5%, -5% tolerance; requires 1µF and 0.1µF bypass capacitors to ground.
32 RX_CLK output RGMII receive clock output at 2.5MHz (10Mbps), 25MHz (100Mbps), or 125MHz (1000Mbps) depending on link speed.
33 SGMII_COP output SGMII differential receive clock positive output at 625MHz (also RX_D0 in RGMII mode); AC coupled via 0.1µF capacitor.
34 SGMII_CON output SGMII differential receive clock negative output at 625MHz (also RX_D1 in RGMII mode); AC coupled via 0.1µF capacitor with internal pull-down.
35 SGMII_SOP output SGMII differential receive data positive output (also RX_D2 in RGMII mode); AC coupled via 0.1µF capacitor with internal pull-down.
36 SGMII_SON output SGMII differential receive data negative output (also RX_D3 in RGMII mode); AC coupled via 0.1µF capacitor with internal pull-down.
37 TX_CTRL input RGMII transmit control signal encoding GMII transmit enable and error on dual GTX_CLK edges for MAC-to-PHY.
38 RX_CTRL output RGMII receive control signal merging receive valid and receive error on RX_CLK dual edges for PHY-to-MAC with internal pull-down.
39 GPIO_0 output Programmable general-purpose output with function selectable via GPIO_MUX_CTRL register (e.g., WOL, SFD, energy detect).
40 GPIO_1 output Programmable general-purpose output with function selectable via GPIO_MUX_CTRL register (e.g., WOL, SFD, energy detect).
41 VDDIO power_in I/O power supply selectable as 3.3V, 2.5V, or 1.8V with ±5% tolerance; requires 1µF and 0.1µF bypass capacitors.
42 VDD1P0 power_in 1V analog power supply with +15.5%, -5% tolerance; requires 1µF and 0.1µF bypass capacitors to ground.
43 RESET_N input Active-low hardware reset input requiring minimum 1µs low pulse to initialize registers to defaults and relatch strap configuration with internal pull-up.
44 INT/PWDN bidirectional Configurable as active-low power-down input (default) or open-drain interrupt output (requires 2.2kΩ external pull-up to VDDIO) with internal pull-up.
45 LED_2 output LED interface pin 2 indicating receive/transmit activity by default; function configurable via LEDCR1[11:8] register bits with strapping capability.
46 LED_1 output LED interface pin 1 indicating 1000BASE-T link establishment by default; function configurable via LEDCR1[7:4] register bits with strapping capability.
47 LED_0 output LED interface pin 0 indicating link establishment by default; function configurable via LEDCR1[3:0] register bits with strapping capability for SGMII enable.
48 VDDA1P8 power_in 1.8V analog power supply with ±5% tolerance; internal generation by default or accept external 1.8V with 1µF and 0.1µF bypass capacitors.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: DP83867ISRGZT
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: dp83867isrgzt-etched.step / dp83867isrgzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83867isrgzt.step / dp83867isrgzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (127 pp, sha256 101dd83b84e239fd, retrieved 2026-10-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF