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docs	dp83867isrgzr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
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dp83867isrgzr-etched.fit.json	dp83867isrgzr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
dp83867isrgzr-etched.glb	dp83867isrgzr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
dp83867isrgzr-etched.step	dp83867isrgzr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
dp83867isrgzr.glb	Publish 0.1.0 · Ray	6d ago
dp83867isrgzr.kicad_mod	Publish 0.1.0 · Ray	6d ago
dp83867isrgzr.kicad_sym	Publish 0.1.0 · Ray	6d ago
dp83867isrgzr.lbr	Publish 0.1.0 · Ray	6d ago
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README.md	Initial commit: component/dp83867isrgzr · Ray	6d ago

DP83867ISRGZR

Texas Instruments · Ethernet Transceivers · VQFN-48-EP(7x7)

DP83867ISRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TD_P_A	passive	Differential transmit/receive pair (positive) for channel A; 100Ω differential impedance required to transformer with 75Ω series resistors and 0.1µF AC coupling capacitor.
2	TD_M_A	passive	Differential transmit/receive pair (negative) for channel A; 100Ω differential impedance required to transformer with 75Ω series resistors and 0.1µF AC coupling capacitor.
3	VDDA2P5	power_in	2.5V analog power supply (±5%); requires 1µF and 0.1µF bypass capacitors to ground.
4	TD_P_B	passive	Differential transmit/receive pair (positive) for channel B; 100Ω differential impedance required to transformer with 75Ω series resistors and 0.1µF AC coupling capacitor.
5	TD_M_B	passive	Differential transmit/receive pair (negative) for channel B; 100Ω differential impedance required to transformer with 75Ω series resistors and 0.1µF AC coupling capacitor.
6	VDD1P0	power_in	1V analog power supply (+15.5%, -5%); requires 1µF and 0.1µF bypass capacitors to ground.
7	TD_P_C	passive	Differential transmit/receive pair (positive) for channel C; 100Ω differential impedance required to transformer with 75Ω series resistors and 0.1µF AC coupling capacitor.
8	TD_M_C	passive	Differential transmit/receive pair (negative) for channel C; 100Ω differential impedance required to transformer with 75Ω series resistors and 0.1µF AC coupling capacitor.
9	VDDA2P5	power_in	2.5V analog power supply (±5%); requires 1µF and 0.1µF bypass capacitors to ground.
10	TD_P_D	passive	Differential transmit/receive pair (positive) for channel D; 100Ω differential impedance required to transformer with 75Ω series resistors and 0.1µF AC coupling capacitor.
11	TD_M_D	passive	Differential transmit/receive pair (negative) for channel D; 100Ω differential impedance required to transformer with 75Ω series resistors and 0.1µF AC coupling capacitor.
12	RBIAS	passive	Bias resistor connection pad; connect 11kΩ ±1% resistor to ground for receiver biasing.
13	VDDA1P8	power_in	1.8V analog power supply (±5%); no external connection required if internal source used; if external 1.8V source used, requires 1µF and 0.1µF bypass capacitors to ground.
14	XO	output	Crystal oscillator output for 25MHz crystal; leave floating if external clock oscillator is used.
15	XI	input	Crystal or oscillator input; accepts 25MHz reference clock (±50ppm) with 1.5-1.9Vpp amplitude.
16	MDC	input	Management Data Clock input for MDIO serial management interface; synchronous clock to MDIO data with maximum frequency 25MHz, no minimum required.
17	MDIO	bidirectional	Management Data I/O bidirectional pin for IEEE 802.3 serial management; requires external 1.5kΩ to 2.2kΩ pull-up resistor to VDDIO.
18	CLK_OUT	output	Clock output pin; outputs 25MHz reference, 125MHz recovered, or 25MHz recovered clock depending on I/O configuration register settings.
19	VDDIO	power_in	I/O power supply for MAC interface; 1.8V (±5%), 2.5V (±5%), or 3.3V (±5%); requires 1µF and 0.1µF bypass capacitors to ground.
20	JTAG_CLK	input	JTAG test clock input per IEEE 1149.1; master clock for test logic with maximum frequency 2.5MHz; internal pull-up.
21	JTAG_TDO	output	JTAG test data output per IEEE 1149.1; outputs latest test results scanned from device test logic.
22	JTAG_TMS	input	JTAG test mode select per IEEE 1149.1; controls TAP controller state machine; internal pull-up; TI recommends holding high with 3 clock cycles to reset JTAG.
23	JTAG_TDI	input	JTAG test data input per IEEE 1149.1; accepts test data scanned into device; internal pull-up.
24	VDD1P0	power_in	1V analog power supply (+15.5%, -5%); requires 1µF and 0.1µF bypass capacitors to ground.
25	TX_D3	input	Transmit data bit 3; in RGMII mode transfers data from MAC to PHY synchronous to GTX_CLK; in SGMII mode functions as SGMII_SOP differential data output.
26	TX_D2	input	Transmit data bit 2; in RGMII mode transfers data from MAC to PHY synchronous to GTX_CLK; in SGMII mode functions as SGMII_SIN differential data input.
27	TX_D1	input	Transmit data bit 1 in RGMII mode; synchronous to GTX_CLK; in SGMII mode functions as SGMII_SIP differential input requiring 0.1µF AC coupling capacitor to MAC.
28	TX_D0	input	Transmit data bit 0 in RGMII mode; synchronous to GTX_CLK; in SGMII mode functions as SGMII_SIN differential input requiring 0.1µF AC coupling capacitor to MAC.
29	GTX_CLK	input	RGMII transmit clock input; continuous 125MHz clock from MAC in 1000Mbps mode; recovers clock edges for data timing in 10/100Mbps modes.
30	VDDIO	power_in	I/O power supply for MAC interface; 1.8V (±5%), 2.5V (±5%), or 3.3V (±5%); requires 1µF and 0.1µF bypass capacitors to ground.
31	VDD1P0	power_in	1V analog power supply (+15.5%, -5%); requires 1µF and 0.1µF bypass capacitors to ground.
32	RX_CLK	output	RGMII receive clock output; recovered receive clock at 2.5MHz (10Mbps), 25MHz (100Mbps), or 125MHz (1000Mbps) depending on link speed.
33	RX_D0	output	Receive data bit 0 in RGMII mode; transfers data from PHY to MAC synchronous to RX_CLK; in SGMII mode functions as SGMII_COP differential clock output.
34	RX_D1	output	Receive data bit 1 in RGMII mode; transfers data from PHY to MAC synchronous to RX_CLK; in SGMII mode functions as SGMII_CON differential clock output.
35	RX_D2	output	Receive data bit 2 in RGMII mode; transfers data from PHY to MAC synchronous to RX_CLK; in SGMII mode functions as SGMII_SOP differential data output.
36	RX_D3	output	Receive data bit 3 in RGMII mode; transfers data from PHY to MAC synchronous to RX_CLK; in SGMII mode functions as SGMII_SON differential data output.
37	TX_CTRL	input	RGMII transmit control pin; encodes GMII TX_EN and TX_ER on GTX_CLK dual edges in 1000Mbps mode; multiplexed in 10/100Mbps modes.
38	RX_CTRL	output	RGMII receive control pin; encodes RXDV and RXERR on RX_CLK dual edges; internal pull-down; must be strapped to mode 3 or 4 for proper operation.
39	GPIO_0	output	General-purpose I/O pin with configurable output function via GPIO_MUX_CTRL register; default outputs RX_ER signal; internal pull-down.
40	GPIO_1	output	General-purpose I/O pin with configurable output function via GPIO_MUX_CTRL register; supports multiple selectable outputs; internal pull-down.
41	VDDIO	power_in	I/O power supply for MAC interface; 1.8V (±5%), 2.5V (±5%), or 3.3V (±5%); requires 1µF and 0.1µF bypass capacitors to ground.
42	VDD1P0	power_in	1V analog power supply (+15.5%, -5%); requires 1µF and 0.1µF bypass capacitors to ground.
43	RESET_N	input	Active-low hardware reset input with internal pull-up; minimum pulse width 1µs; re-initializes all registers to default and re-latches hardware configuration pins.
44	INT/PWDN	bidirectional	Dual-function pin with internal pull-up; default is active-low power-down input; can be configured as open-drain interrupt output via CFG3 register INT_OE bit; TI recommends 2.2kΩ external pull-up resistor.
45	LED_2	output	LED output pin; default indicates transmit/receive activity; output function configurable via LEDCR1[11:8] bits; internal pull-down.
46	LED_1	output	LED output pin; default indicates 1000BASE-T link established; output function configurable via LEDCR1[7:4] bits; internal pull-down.
47	LED_0	output	LED output pin; default indicates link established; output function configurable via LEDCR1[3:0] bits; internal pull-down.
48	VDDA1P8	power_in	1.8V analog power supply (±5%); no external connection required if internal source used; if external 1.8V source used, requires 1µF and 0.1µF bypass capacitors to ground.
DAP	GND	power_in	Die Attach Pad; ground connection; must be soldered to PCB ground plane for proper thermal performance and mechanical support.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-48-EP(7x7)
Category	Interface
Pins	49

CAD (KiCad official)

Symbol: DP83867ISRGZR
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: dp83867isrgzr-etched.step / dp83867isrgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83867isrgzr.step / dp83867isrgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (127 pp, sha256 101dd83b84e239fd, retrieved 2026-09-29, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF