component
DP83867IRRGZT
Public Made by Adomby adom
Texas Instruments Ethernet Transceivers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DP83867IRRGZT
Texas Instruments · Ethernet Transceivers · VQFN-48-EP(7x7)
DP83867IRRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TD_P_A | passive | Media-dependent interface channel A, positive differential line, connected through the external magnetics to the RJ-45; channels A and B are sufficient for 10/100 operation. |
| 2 | TD_M_A | passive | Media-dependent interface channel A, negative differential line, connected through the external magnetics to the RJ-45; channels A and B are sufficient for 10/100 operation. |
| 3 | VDDA2P5 | power_in | 2.5 V analog supply, recommended 2.375 V to 2.625 V; decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 4 | TD_P_B | passive | Media-dependent interface channel B, positive differential line, connected through the external magnetics to the RJ-45. |
| 5 | TD_M_B | passive | Media-dependent interface channel B, negative differential line, connected through the external magnetics to the RJ-45. |
| 6 | VDD1P0 | power_in | 1.0 V analog core supply on the RGZ package, recommended 0.95 V to 1.155 V; decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 7 | TD_P_C | passive | Media-dependent interface channel C, positive differential line, used only in 1000BASE-T mode. |
| 8 | TD_M_C | passive | Media-dependent interface channel C, negative differential line, used only in 1000BASE-T mode. |
| 9 | VDDA2P5 | power_in | 2.5 V analog supply, recommended 2.375 V to 2.625 V; decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 10 | TD_P_D | passive | Media-dependent interface channel D, positive differential line, used only in 1000BASE-T mode. |
| 11 | TD_M_D | passive | Media-dependent interface channel D, negative differential line, used only in 1000BASE-T mode. |
| 12 | RBIAS | passive | Bias resistor connection; an 11 kΩ ±1% resistor must be connected from this pin to GND. |
| 13 | VDDA1P8 | power_in | 1.8 V analog supply (±5%, 1.71 V to 1.89 V); no external supply is required, and the pin must not be connected to any circuit when unused in the dual-supply configuration. |
| 14 | XO | output | 25 MHz crystal second terminal; leave unconnected when a clock oscillator drives XI. |
| 15 | XI | input | 25 MHz oscillator or crystal input, ±50 ppm; for 3.3 V or 2.5 V clock sources a capacitive divider is recommended. |
| 16 | MDC | input | Management data clock for MDIO serial management, maximum 25 MHz with no minimum; may be asynchronous to the MAC clocks. |
| 17 | MDIO | bidirectional | Management data input/output; requires an external pull-up of 1.5 kΩ per IEEE, with 2.2 kΩ acceptable. |
| 18 | CLK_OUT | output | Clock output, synchronous to XI by default and configurable through IO_MUX_CFG to recovered or transmit clocks. |
| 19 | VDDIO | power_in | I/O supply of 1.8 V, 2.5 V or 3.3 V (±5%); decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 20 | JTAG_CLK | input | IEEE 1149.1 JTAG test clock input with internal pull-up, supporting a maximum clock frequency of 2.5 MHz. |
| 21 | JTAG_TDO | output | IEEE 1149.1 JTAG test data output through which the latest test results are scanned out. |
| 22 | JTAG_TMS | input | IEEE 1149.1 JTAG test mode select with internal pull-up, providing sequencing for the 16-state TAP controller. |
| 23 | JTAG_TDI | input | IEEE 1149.1 JTAG test data input with internal pull-up, through which test data is scanned into the device. |
| 24 | VDD1P0 | power_in | 1.0 V analog core supply on the RGZ package, recommended 0.95 V to 1.155 V; decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 25 | TX_D3 | input | MAC transmit data bit 3, synchronous to GTX_CLK in GMII/RGMII mode or TX_CLK in MII mode; internal pull-down. |
| 26 | TX_D2 | input | MAC transmit data bit 2, synchronous to GTX_CLK in GMII/RGMII mode or TX_CLK in MII mode; internal pull-down. |
| 27 | TX_D1 | input | MAC transmit data bit 1, synchronous to GTX_CLK in GMII/RGMII mode or TX_CLK in MII mode; internal pull-down. |
| 28 | TX_D0 | input | MAC transmit data bit 0, synchronous to GTX_CLK in GMII/RGMII mode or TX_CLK in MII mode; internal pull-down. |
| 29 | GTX_CLK | input | Continuous transmit clock supplied by the MAC for GMII and RGMII, nominally 125 MHz. |
| 30 | VDDIO | power_in | I/O supply of 1.8 V, 2.5 V or 3.3 V (±5%); decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 31 | VDD1P0 | power_in | 1.0 V analog core supply on the RGZ package, recommended 0.95 V to 1.155 V; decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 32 | RX_CLK | output | Recovered receive clock: 2.5 MHz at 10 Mbps, 25 MHz at 100 Mbps, and 125 MHz in 1000 Mbps GMII/RGMII mode. |
| 33 | RX_D0 | bidirectional | Receive data bit 0 from PHY to MAC, synchronous to RX_CLK; this pin is also a 4-level strap input (PHY_ADD1/PHY_ADD0) sampled at power-up or reset. |
| 34 | RX_D1 | output | Receive data bit 1 from PHY to MAC, synchronous to RX_CLK; internal pull-down. |
| 35 | RX_D2 | bidirectional | Receive data bit 2 from PHY to MAC, synchronous to RX_CLK; this pin is also a 4-level strap input (PHY_ADD3/PHY_ADD2) sampled at power-up or reset. |
| 36 | RX_D3 | output | Receive data bit 3 from PHY to MAC, synchronous to RX_CLK; internal pull-down. |
| 37 | TX_EN/TX_CTRL | input | In MII/GMII mode this is the active-high transmit enable from the MAC; in RGMII mode it carries TX_CTRL, combining TX_EN and TX_ER on both clock edges; internal pull-down. |
| 38 | RX_DV/RX_CTRL | bidirectional | In MII/GMII mode this is the active-high receive data valid; in RGMII mode it carries RXDV_ER, combining RX_DV and RX_ER on both RX_CLK edges; this pin must be strapped to mode 3 or 4. |
| 39 | GPIO_0 | bidirectional | General-purpose multifunction configurable I/O set through GPIO_MUX_CTRL; also a 4-level strap input (RGMII clock skew RX[0]). |
| 40 | GPIO_1 | bidirectional | General-purpose multifunction configurable I/O set through GPIO_MUX_CTRL; also a 4-level strap input (RGMII clock skew RX[2]/RX[1]). |
| 41 | VDDIO | power_in | I/O supply of 1.8 V, 2.5 V or 3.3 V (±5%); decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 42 | VDD1P0 | power_in | 1.0 V analog core supply on the RGZ package, recommended 0.95 V to 1.155 V; decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 43 | RESET_N | input | Active-low reset with internal pull-up that reinitializes all registers to default; the input must be held low for at least 1 µs. |
| 44 | INT/PWDN | bidirectional | Default active-low power-down input with internal pull-up; when programmed as interrupt output it is open-drain and a 2.2 kΩ pull-up to VDDIO is recommended. |
| 45 | LED_2 | bidirectional | LED output, default receive/transmit activity, configurable through LEDCR1; also a 4-level strap pin on the RGZ package. |
| 46 | LED_1 | bidirectional | LED output, default 1000BASE-T link established, configurable through LEDCR1; also a 4-level strap pin. |
| 47 | LED_0 | bidirectional | LED output, default link established, configurable through LEDCR1; also a 4-level strap pin. |
| 48 | VDDA1P8 | power_in | 1.8 V analog supply (±5%, 1.71 V to 1.89 V); no external supply is required, and the pin must not be connected to any circuit when unused in the dual-supply configuration. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Interface |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
DP83867IRRGZT - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
dp83867irrgzt-etched.step/dp83867irrgzt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dp83867irrgzt.step/dp83867irrgzt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (136 pp, sha256
86c425421d9ee17a, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DP83867IRRGZT
**Texas Instruments** · Ethernet Transceivers · VQFN-48-EP(7x7)
DP83867IRRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TD_P_A | passive | Media-dependent interface channel A, positive differential line, connected through the external magnetics to the RJ-45; channels A and B are sufficient for 10/100 operation. |
| 2 | TD_M_A | passive | Media-dependent interface channel A, negative differential line, connected through the external magnetics to the RJ-45; channels A and B are sufficient for 10/100 operation. |
| 3 | VDDA2P5 | power_in | 2.5 V analog supply, recommended 2.375 V to 2.625 V; decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 4 | TD_P_B | passive | Media-dependent interface channel B, positive differential line, connected through the external magnetics to the RJ-45. |
| 5 | TD_M_B | passive | Media-dependent interface channel B, negative differential line, connected through the external magnetics to the RJ-45. |
| 6 | VDD1P0 | power_in | 1.0 V analog core supply on the RGZ package, recommended 0.95 V to 1.155 V; decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 7 | TD_P_C | passive | Media-dependent interface channel C, positive differential line, used only in 1000BASE-T mode. |
| 8 | TD_M_C | passive | Media-dependent interface channel C, negative differential line, used only in 1000BASE-T mode. |
| 9 | VDDA2P5 | power_in | 2.5 V analog supply, recommended 2.375 V to 2.625 V; decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 10 | TD_P_D | passive | Media-dependent interface channel D, positive differential line, used only in 1000BASE-T mode. |
| 11 | TD_M_D | passive | Media-dependent interface channel D, negative differential line, used only in 1000BASE-T mode. |
| 12 | RBIAS | passive | Bias resistor connection; an 11 kΩ ±1% resistor must be connected from this pin to GND. |
| 13 | VDDA1P8 | power_in | 1.8 V analog supply (±5%, 1.71 V to 1.89 V); no external supply is required, and the pin must not be connected to any circuit when unused in the dual-supply configuration. |
| 14 | XO | output | 25 MHz crystal second terminal; leave unconnected when a clock oscillator drives XI. |
| 15 | XI | input | 25 MHz oscillator or crystal input, ±50 ppm; for 3.3 V or 2.5 V clock sources a capacitive divider is recommended. |
| 16 | MDC | input | Management data clock for MDIO serial management, maximum 25 MHz with no minimum; may be asynchronous to the MAC clocks. |
| 17 | MDIO | bidirectional | Management data input/output; requires an external pull-up of 1.5 kΩ per IEEE, with 2.2 kΩ acceptable. |
| 18 | CLK_OUT | output | Clock output, synchronous to XI by default and configurable through IO_MUX_CFG to recovered or transmit clocks. |
| 19 | VDDIO | power_in | I/O supply of 1.8 V, 2.5 V or 3.3 V (±5%); decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 20 | JTAG_CLK | input | IEEE 1149.1 JTAG test clock input with internal pull-up, supporting a maximum clock frequency of 2.5 MHz. |
| 21 | JTAG_TDO | output | IEEE 1149.1 JTAG test data output through which the latest test results are scanned out. |
| 22 | JTAG_TMS | input | IEEE 1149.1 JTAG test mode select with internal pull-up, providing sequencing for the 16-state TAP controller. |
| 23 | JTAG_TDI | input | IEEE 1149.1 JTAG test data input with internal pull-up, through which test data is scanned into the device. |
| 24 | VDD1P0 | power_in | 1.0 V analog core supply on the RGZ package, recommended 0.95 V to 1.155 V; decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 25 | TX_D3 | input | MAC transmit data bit 3, synchronous to GTX_CLK in GMII/RGMII mode or TX_CLK in MII mode; internal pull-down. |
| 26 | TX_D2 | input | MAC transmit data bit 2, synchronous to GTX_CLK in GMII/RGMII mode or TX_CLK in MII mode; internal pull-down. |
| 27 | TX_D1 | input | MAC transmit data bit 1, synchronous to GTX_CLK in GMII/RGMII mode or TX_CLK in MII mode; internal pull-down. |
| 28 | TX_D0 | input | MAC transmit data bit 0, synchronous to GTX_CLK in GMII/RGMII mode or TX_CLK in MII mode; internal pull-down. |
| 29 | GTX_CLK | input | Continuous transmit clock supplied by the MAC for GMII and RGMII, nominally 125 MHz. |
| 30 | VDDIO | power_in | I/O supply of 1.8 V, 2.5 V or 3.3 V (±5%); decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 31 | VDD1P0 | power_in | 1.0 V analog core supply on the RGZ package, recommended 0.95 V to 1.155 V; decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 32 | RX_CLK | output | Recovered receive clock: 2.5 MHz at 10 Mbps, 25 MHz at 100 Mbps, and 125 MHz in 1000 Mbps GMII/RGMII mode. |
| 33 | RX_D0 | bidirectional | Receive data bit 0 from PHY to MAC, synchronous to RX_CLK; this pin is also a 4-level strap input (PHY_ADD1/PHY_ADD0) sampled at power-up or reset. |
| 34 | RX_D1 | output | Receive data bit 1 from PHY to MAC, synchronous to RX_CLK; internal pull-down. |
| 35 | RX_D2 | bidirectional | Receive data bit 2 from PHY to MAC, synchronous to RX_CLK; this pin is also a 4-level strap input (PHY_ADD3/PHY_ADD2) sampled at power-up or reset. |
| 36 | RX_D3 | output | Receive data bit 3 from PHY to MAC, synchronous to RX_CLK; internal pull-down. |
| 37 | TX_EN/TX_CTRL | input | In MII/GMII mode this is the active-high transmit enable from the MAC; in RGMII mode it carries TX_CTRL, combining TX_EN and TX_ER on both clock edges; internal pull-down. |
| 38 | RX_DV/RX_CTRL | bidirectional | In MII/GMII mode this is the active-high receive data valid; in RGMII mode it carries RXDV_ER, combining RX_DV and RX_ER on both RX_CLK edges; this pin must be strapped to mode 3 or 4. |
| 39 | GPIO_0 | bidirectional | General-purpose multifunction configurable I/O set through GPIO_MUX_CTRL; also a 4-level strap input (RGMII clock skew RX[0]). |
| 40 | GPIO_1 | bidirectional | General-purpose multifunction configurable I/O set through GPIO_MUX_CTRL; also a 4-level strap input (RGMII clock skew RX[2]/RX[1]). |
| 41 | VDDIO | power_in | I/O supply of 1.8 V, 2.5 V or 3.3 V (±5%); decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 42 | VDD1P0 | power_in | 1.0 V analog core supply on the RGZ package, recommended 0.95 V to 1.155 V; decouple each pin to GND with 1 µF and 0.1 µF capacitors. |
| 43 | RESET_N | input | Active-low reset with internal pull-up that reinitializes all registers to default; the input must be held low for at least 1 µs. |
| 44 | INT/PWDN | bidirectional | Default active-low power-down input with internal pull-up; when programmed as interrupt output it is open-drain and a 2.2 kΩ pull-up to VDDIO is recommended. |
| 45 | LED_2 | bidirectional | LED output, default receive/transmit activity, configurable through LEDCR1; also a 4-level strap pin on the RGZ package. |
| 46 | LED_1 | bidirectional | LED output, default 1000BASE-T link established, configurable through LEDCR1; also a 4-level strap pin. |
| 47 | LED_0 | bidirectional | LED output, default link established, configurable through LEDCR1; also a 4-level strap pin. |
| 48 | VDDA1P8 | power_in | 1.8 V analog supply (±5%, 1.71 V to 1.89 V); no external supply is required, and the pin must not be connected to any circuit when unused in the dual-supply configuration. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Interface |
| Pins | 49 |
## CAD (KiCad official)
- Symbol: `DP83867IRRGZT`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `dp83867irrgzt-etched.step` / `dp83867irrgzt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83867irrgzt.step` / `dp83867irrgzt.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83867ir) (136 pp, sha256 `86c425421d9ee17a`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dp83867irrgzt-datasheet.pdf)