component
DP83867ERGZR
Public Made by Adomby adom
Texas Instruments Interface - Specialized, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# DP83867ERGZR++**Texas Instruments** · Interface - Specialized · VQFN-48-EP(7x7)++DP83867ERGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TD_P_A | passive | Transmit/receive differential signal pair A positive for 1000BASE-T physical layer connection via transformer. |+| 2 | TD_M_A | passive | Transmit/receive differential signal pair A negative for 1000BASE-T physical layer connection via transformer. |+| 3 | VDDA2P5 | power_in | 2.5V analog power supply with ±5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin. |+| 4 | TD_P_B | passive | Transmit/receive differential signal pair B positive for 1000BASE-T physical layer connection via transformer. |+| 5 | TD_M_B | passive | Transmit/receive differential signal pair B negative for 1000BASE-T physical layer connection via transformer. |+| 6 | VDD1P0 | power_in | 1V analog power supply with +15.5% and -5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin. |+| 7 | TD_P_C | passive | Transmit/receive differential signal pair C positive for 1000BASE-T physical layer connection via transformer. |+| 8 | TD_M_C | passive | Transmit/receive differential signal pair C negative for 1000BASE-T physical layer connection via transformer. |+| 9 | VDDA2P5 | power_in | 2.5V analog power supply with ±5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin. |+| 10 | TD_P_D | passive | Transmit/receive differential signal pair D positive for 1000BASE-T physical layer connection via transformer. |+| 11 | TD_M_D | passive | Transmit/receive differential signal pair D negative for 1000BASE-T physical layer connection via transformer. |+| 12 | RBIAS | passive | Bias resistor connection terminal; requires external 11kΩ ±1% resistor to ground for impedance network tuning. |+| 13 | VDDA1P8 | power_in | 1.8V analog power supply with ±5% tolerance; no external power required in dual-supply mode, but 1µF and 0.1µF capacitors to ground recommended if external supply used. |+| 14 | XO | output | Crystal oscillator output terminal for 25MHz crystal; keep floating if external clock source is used on XI pin. |+| 15 | XI | input | Crystal oscillator input terminal accepting 25MHz oscillator or crystal with 50ppm frequency accuracy and 1.5V to 1.9V amplitude. |+| 16 | MDC | input | Management data clock input synchronized to MDIO data; maximum clock rate is 25MHz with no minimum requirement. |+| 17 | MDIO | bidirectional | Bidirectional management data I/O terminal requiring external 1.5kΩ to 2.2kΩ pull-up resistor to VDDIO for IEEE 802.3 compliance. |+| 18 | CLK_OUT | output | Programmable clock output providing 25MHz, 125MHz, or divide-by-5 derived clock synchronized to XI, RX, or TX reference per IO_MUX_CFG register. |+| 19 | VDDIO | power_in | I/O power supply selectable as 3.3V (±5%), 2.5V (±5%), or 1.8V (±5%); requires 1µF and 0.1µF decoupling capacitors to ground on each pin. |+| 20 | JTAG_CLK | input | JTAG test clock input compliant with IEEE 1149.1 standard supporting maximum 2.5MHz clock frequency; requires internal pull-up resistor. |+| 21 | JTAG_TDO | output | JTAG test data output pin providing serial scan data from IEEE 1149.1 compliant test interface. |+| 22 | JTAG_TMS | input | JTAG test mode select input controlling TAP controller state machine per IEEE 1149.1; requires internal pull-up and recommended held high with 3 clock pulses for reset. |+| 23 | JTAG_TDI | input | JTAG test data input pin for serial scan input compliance with IEEE 1149.1 standard; requires internal pull-up resistor. |+| 24 | VDD1P0 | power_in | 1V analog power supply with +15.5% and -5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin. |+| 25 | TX_D3 | input | RGMII transmit data bit 3 synchronized to GTX_CLK; transfers data from MAC to PHY in RGMII mode at 10/100/1000Mbps. |+| 26 | TX_D2 | input | RGMII transmit data bit 2 synchronized to GTX_CLK; transfers data from MAC to PHY in RGMII mode at 10/100/1000Mbps. |+| 27 | TX_D1 | input | RGMII transmit data bit 1 synchronized to GTX_CLK; transfers data from MAC to PHY in RGMII mode, or functions as SGMII_SIP differential pair in SGMII mode. |+| 28 | TX_D0 | input | RGMII transmit data bit 0 synchronized to GTX_CLK; transfers data from MAC to PHY in RGMII mode, or functions as SGMII_SIN differential pair in SGMII mode. |+| 29 | GTX_CLK | input | RGMII transmit clock input from MAC with nominal 125MHz frequency for 1000Mbps; scaled to 25MHz at 100Mbps and 2.5MHz at 10Mbps operation. |+| 30 | VDDIO | power_in | I/O power supply selectable as 3.3V (±5%), 2.5V (±5%), or 1.8V (±5%); requires 1µF and 0.1µF decoupling capacitors to ground on each pin. |+| 31 | VDD1P0 | power_in | 1V analog power supply with +15.5% and -5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin. |+| 32 | RX_CLK | output | RGMII recovered receive clock output frequency dependent on link speed: 2.5MHz (10Mbps), 25MHz (100Mbps), or 125MHz (1000Mbps). |+| 33 | RX_D0 | output | RGMII receive data bit 0 synchronized to RX_CLK; transfers data from PHY to MAC in RGMII mode, or functions as SGMII_COP differential pair in SGMII mode. |+| 34 | RX_D1 | output | RGMII receive data bit 1 synchronized to RX_CLK; transfers data from PHY to MAC in RGMII mode, or functions as SGMII_CON differential pair in SGMII mode. |+| 35 | RX_D2 | output | RGMII receive data bit 2 synchronized to RX_CLK; transfers data from PHY to MAC in RGMII mode, or functions as SGMII_SOP differential pair in SGMII mode. |+| 36 | RX_D3 | output | RGMII receive data bit 3 synchronized to RX_CLK; transfers data from PHY to MAC in RGMII mode, or functions as SGMII_SON differential pair in SGMII mode. |+| 37 | TX_CTRL | input | RGMII transmit control combining GMII transmit enable and error signals using dual-edge clocking on GTX_CLK for 1000Mbps operation. |+| 38 | RX_CTRL | output | RGMII receive control combining receive data valid and error signals RXDV_ER using dual-edge clocking on RX_CLK; serves as configuration pin in Strap mode. |+| 39 | GPIO_0 | output | Configurable general-purpose I/O providing multipurpose signal selection via GPIO_MUX_CTRL register; serves as RGMII RX clock delay configuration pin in Strap mode. |+| 40 | GPIO_1 | output | Configurable general-purpose I/O providing multipurpose signal selection via GPIO_MUX_CTRL register; serves as RGMII clock delay configuration pins in Strap mode. |+| 41 | VDDIO | power_in | I/O power supply selectable as 3.3V (±5%), 2.5V (±5%), or 1.8V (±5%); requires 1µF and 0.1µF decoupling capacitors to ground on each pin. |+| 42 | VDD1P0 | power_in | 1V analog power supply with +15.5% and -5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin. |+| 43 | RESET_N | input | Active-low asynchronous reset input requiring minimum 1µs low pulse; initializes all internal registers to default state and relatches hardware configuration pins. |+| 44 | INT/PWDN | bidirectional | Dual-function open-drain output for interrupt signaling or active-low input for power-down mode; requires external 2.2kΩ pull-up to VDDIO when used as interrupt output. |+| 45 | LED_2 | output | Configurable LED output pin providing activity or link status indication; default function shows transmit/receive activity with programmable LEDCR1 configuration. |+| 46 | LED_1 | output | Configurable LED output pin providing link status indication; default function shows 1000BASE-T link establishment with programmable LEDCR1 configuration. |+| 47 | LED_0 | output | Configurable LED output pin providing link establishment indication; default function shows active link status with programmable LEDCR1 configuration; serves as SGMII enable Strap pin. |+| 48 | VDDA1P8 | power_in | 1.8V analog power supply with ±5% tolerance; no external power required in dual-supply mode, but 1µF and 0.1µF capacitors to ground recommended if external supply used. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Interface |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `DP83867ERGZR`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `dp83867ergzr-etched.step` / `dp83867ergzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83867ergzr.step` / `dp83867ergzr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83867is) (127 pp, sha256 `101dd83b84e239fd`, retrieved 2026-09-21, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dp83867ergzr-datasheet.pdf)
page.jsonadded+390@@ -0,0 +1,390 @@+{+ "slug": "dp83867ergzr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Interface - Specialized, VQFN-48-EP(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "dp83867ergzr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dp83867ergzr.kicad_sym",+ "dp83867ergzr.kicad_mod",+ "dp83867ergzr.glb",+ "dp83867ergzr.step",+ "dp83867ergzr.lbr",+ "docs/hero.png",+ "docs/dp83867ergzr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DP83867ERGZR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "Interface",+ "subcategory": "Interface - Specialized",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dp83867is",+ "parts": {+ "symbol": "dp83867ergzr.kicad_sym",+ "footprint": "dp83867ergzr.kicad_mod",+ "model_3d": "dp83867ergzr-etched.glb",+ "model_3d_plain": "dp83867ergzr.glb",+ "model_3d_step": "dp83867ergzr-etched.step",+ "model_3d_step_plain": "dp83867ergzr.step",+ "lbr": "dp83867ergzr.lbr"+ },+ "distributor_links": {+ "lcsc": "C913839"+ },+ "pins": [+ {+ "number": "1",+ "name": "TD_P_A",+ "type": "passive",+ "description": "Transmit/receive differential signal pair A positive for 1000BASE-T physical layer connection via transformer."+ },+ {+ "number": "2",+ "name": "TD_M_A",+ "type": "passive",+ "description": "Transmit/receive differential signal pair A negative for 1000BASE-T physical layer connection via transformer."+ },+ {+ "number": "3",+ "name": "VDDA2P5",+ "type": "power_in",+ "description": "2.5V analog power supply with ±5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin."+ },+ {+ "number": "4",+ "name": "TD_P_B",+ "type": "passive",+ "description": "Transmit/receive differential signal pair B positive for 1000BASE-T physical layer connection via transformer."+ },+ {+ "number": "5",+ "name": "TD_M_B",+ "type": "passive",+ "description": "Transmit/receive differential signal pair B negative for 1000BASE-T physical layer connection via transformer."+ },+ {+ "number": "6",+ "name": "VDD1P0",+ "type": "power_in",+ "description": "1V analog power supply with +15.5% and -5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin."+ },+ {+ "number": "7",+ "name": "TD_P_C",+ "type": "passive",+ "description": "Transmit/receive differential signal pair C positive for 1000BASE-T physical layer connection via transformer."+ },+ {+ "number": "8",+ "name": "TD_M_C",+ "type": "passive",+ "description": "Transmit/receive differential signal pair C negative for 1000BASE-T physical layer connection via transformer."+ },+ {+ "number": "9",+ "name": "VDDA2P5",+ "type": "power_in",+ "description": "2.5V analog power supply with ±5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin."+ },+ {+ "number": "10",+ "name": "TD_P_D",+ "type": "passive",+ "description": "Transmit/receive differential signal pair D positive for 1000BASE-T physical layer connection via transformer."+ },+ {+ "number": "11",+ "name": "TD_M_D",+ "type": "passive",+ "description": "Transmit/receive differential signal pair D negative for 1000BASE-T physical layer connection via transformer."+ },+ {+ "number": "12",+ "name": "RBIAS",+ "type": "passive",+ "description": "Bias resistor connection terminal; requires external 11kΩ ±1% resistor to ground for impedance network tuning."+ },+ {+ "number": "13",+ "name": "VDDA1P8",+ "type": "power_in",+ "description": "1.8V analog power supply with ±5% tolerance; no external power required in dual-supply mode, but 1µF and 0.1µF capacitors to ground recommended if external supply used."+ },+ {+ "number": "14",+ "name": "XO",+ "type": "output",+ "description": "Crystal oscillator output terminal for 25MHz crystal; keep floating if external clock source is used on XI pin."+ },+ {+ "number": "15",+ "name": "XI",+ "type": "input",+ "description": "Crystal oscillator input terminal accepting 25MHz oscillator or crystal with 50ppm frequency accuracy and 1.5V to 1.9V amplitude."+ },+ {+ "number": "16",+ "name": "MDC",+ "type": "input",+ "description": "Management data clock input synchronized to MDIO data; maximum clock rate is 25MHz with no minimum requirement."+ },+ {+ "number": "17",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Bidirectional management data I/O terminal requiring external 1.5kΩ to 2.2kΩ pull-up resistor to VDDIO for IEEE 802.3 compliance."+ },+ {+ "number": "18",+ "name": "CLK_OUT",+ "type": "output",+ "description": "Programmable clock output providing 25MHz, 125MHz, or divide-by-5 derived clock synchronized to XI, RX, or TX reference per IO_MUX_CFG register."+ },+ {+ "number": "19",+ "name": "VDDIO",+ "type": "power_in",+ "description": "I/O power supply selectable as 3.3V (±5%), 2.5V (±5%), or 1.8V (±5%); requires 1µF and 0.1µF decoupling capacitors to ground on each pin."+ },+ {+ "number": "20",+ "name": "JTAG_CLK",+ "type": "input",+ "description": "JTAG test clock input compliant with IEEE 1149.1 standard supporting maximum 2.5MHz clock frequency; requires internal pull-up resistor."+ },+ {+ "number": "21",+ "name": "JTAG_TDO",+ "type": "output",+ "description": "JTAG test data output pin providing serial scan data from IEEE 1149.1 compliant test interface."+ },+ {+ "number": "22",+ "name": "JTAG_TMS",+ "type": "input",+ "description": "JTAG test mode select input controlling TAP controller state machine per IEEE 1149.1; requires internal pull-up and recommended held high with 3 clock pulses for reset."+ },+ {+ "number": "23",+ "name": "JTAG_TDI",+ "type": "input",+ "description": "JTAG test data input pin for serial scan input compliance with IEEE 1149.1 standard; requires internal pull-up resistor."+ },+ {+ "number": "24",+ "name": "VDD1P0",+ "type": "power_in",+ "description": "1V analog power supply with +15.5% and -5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin."+ },+ {+ "number": "25",+ "name": "TX_D3",+ "type": "input",+ "description": "RGMII transmit data bit 3 synchronized to GTX_CLK; transfers data from MAC to PHY in RGMII mode at 10/100/1000Mbps."+ },+ {+ "number": "26",+ "name": "TX_D2",+ "type": "input",+ "description": "RGMII transmit data bit 2 synchronized to GTX_CLK; transfers data from MAC to PHY in RGMII mode at 10/100/1000Mbps."+ },+ {+ "number": "27",+ "name": "TX_D1",+ "type": "input",+ "description": "RGMII transmit data bit 1 synchronized to GTX_CLK; transfers data from MAC to PHY in RGMII mode, or functions as SGMII_SIP differential pair in SGMII mode."+ },+ {+ "number": "28",+ "name": "TX_D0",+ "type": "input",+ "description": "RGMII transmit data bit 0 synchronized to GTX_CLK; transfers data from MAC to PHY in RGMII mode, or functions as SGMII_SIN differential pair in SGMII mode."+ },+ {+ "number": "29",+ "name": "GTX_CLK",+ "type": "input",+ "description": "RGMII transmit clock input from MAC with nominal 125MHz frequency for 1000Mbps; scaled to 25MHz at 100Mbps and 2.5MHz at 10Mbps operation."+ },+ {+ "number": "30",+ "name": "VDDIO",+ "type": "power_in",+ "description": "I/O power supply selectable as 3.3V (±5%), 2.5V (±5%), or 1.8V (±5%); requires 1µF and 0.1µF decoupling capacitors to ground on each pin."+ },+ {+ "number": "31",+ "name": "VDD1P0",+ "type": "power_in",+ "description": "1V analog power supply with +15.5% and -5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin."+ },+ {+ "number": "32",+ "name": "RX_CLK",+ "type": "output",+ "description": "RGMII recovered receive clock output frequency dependent on link speed: 2.5MHz (10Mbps), 25MHz (100Mbps), or 125MHz (1000Mbps)."+ },+ {+ "number": "33",+ "name": "RX_D0",+ "type": "output",+ "description": "RGMII receive data bit 0 synchronized to RX_CLK; transfers data from PHY to MAC in RGMII mode, or functions as SGMII_COP differential pair in SGMII mode."+ },+ {+ "number": "34",+ "name": "RX_D1",+ "type": "output",+ "description": "RGMII receive data bit 1 synchronized to RX_CLK; transfers data from PHY to MAC in RGMII mode, or functions as SGMII_CON differential pair in SGMII mode."+ },+ {+ "number": "35",+ "name": "RX_D2",+ "type": "output",+ "description": "RGMII receive data bit 2 synchronized to RX_CLK; transfers data from PHY to MAC in RGMII mode, or functions as SGMII_SOP differential pair in SGMII mode."+ },+ {+ "number": "36",+ "name": "RX_D3",+ "type": "output",+ "description": "RGMII receive data bit 3 synchronized to RX_CLK; transfers data from PHY to MAC in RGMII mode, or functions as SGMII_SON differential pair in SGMII mode."+ },+ {+ "number": "37",+ "name": "TX_CTRL",+ "type": "input",+ "description": "RGMII transmit control combining GMII transmit enable and error signals using dual-edge clocking on GTX_CLK for 1000Mbps operation."+ },+ {+ "number": "38",+ "name": "RX_CTRL",+ "type": "output",+ "description": "RGMII receive control combining receive data valid and error signals RXDV_ER using dual-edge clocking on RX_CLK; serves as configuration pin in Strap mode."+ },+ {+ "number": "39",+ "name": "GPIO_0",+ "type": "output",+ "description": "Configurable general-purpose I/O providing multipurpose signal selection via GPIO_MUX_CTRL register; serves as RGMII RX clock delay configuration pin in Strap mode."+ },+ {+ "number": "40",+ "name": "GPIO_1",+ "type": "output",+ "description": "Configurable general-purpose I/O providing multipurpose signal selection via GPIO_MUX_CTRL register; serves as RGMII clock delay configuration pins in Strap mode."+ },+ {+ "number": "41",+ "name": "VDDIO",+ "type": "power_in",+ "description": "I/O power supply selectable as 3.3V (±5%), 2.5V (±5%), or 1.8V (±5%); requires 1µF and 0.1µF decoupling capacitors to ground on each pin."+ },+ {+ "number": "42",+ "name": "VDD1P0",+ "type": "power_in",+ "description": "1V analog power supply with +15.5% and -5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin."+ },+ {+ "number": "43",+ "name": "RESET_N",+ "type": "input",+ "description": "Active-low asynchronous reset input requiring minimum 1µs low pulse; initializes all internal registers to default state and relatches hardware configuration pins."+ },+ {+ "number": "44",+ "name": "INT/PWDN",+ "type": "bidirectional",+ "description": "Dual-function open-drain output for interrupt signaling or active-low input for power-down mode; requires external 2.2kΩ pull-up to VDDIO when used as interrupt output."+ },+ {+ "number": "45",+ "name": "LED_2",+ "type": "output",+ "description": "Configurable LED output pin providing activity or link status indication; default function shows transmit/receive activity with programmable LEDCR1 configuration."+ },+ {+ "number": "46",+ "name": "LED_1",+ "type": "output",+ "description": "Configurable LED output pin providing link status indication; default function shows 1000BASE-T link establishment with programmable LEDCR1 configuration."+ },+ {+ "number": "47",+ "name": "LED_0",+ "type": "output",+ "description": "Configurable LED output pin providing link establishment indication; default function shows active link status with programmable LEDCR1 configuration; serves as SGMII enable Strap pin."+ },+ {+ "number": "48",+ "name": "VDDA1P8",+ "type": "power_in",+ "description": "1.8V analog power supply with ±5% tolerance; no external power required in dual-supply mode, but 1µF and 0.1µF capacitors to ground recommended if external supply used."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Dual-function pins (27, 28, 33, 34, 35, 36) have both RGMII and SGMII mode names; descriptions show ; Die attach pad (DAP) labeled as GND on package diagram not included in standard pin list; thermal pa; Pins 38, 39, 40 listed as output type but datasheet indicates configuration pin (S) functionality wi",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 127,+ "cost_usd": 1.6985,+ "at": "2026-09-21T21:57:35"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dp83867is",+ "pages": 127,+ "sha256": "101dd83b84e239fd",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}