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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83867ERGZR

Texas Instruments · Interface - Specialized · VQFN-48-EP(7x7)

DP83867ERGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TD_P_A	passive	Transmit/receive differential signal pair A positive for 1000BASE-T physical layer connection via transformer.
2	TD_M_A	passive	Transmit/receive differential signal pair A negative for 1000BASE-T physical layer connection via transformer.
3	VDDA2P5	power_in	2.5V analog power supply with ±5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin.
4	TD_P_B	passive	Transmit/receive differential signal pair B positive for 1000BASE-T physical layer connection via transformer.
5	TD_M_B	passive	Transmit/receive differential signal pair B negative for 1000BASE-T physical layer connection via transformer.
6	VDD1P0	power_in	1V analog power supply with +15.5% and -5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin.
7	TD_P_C	passive	Transmit/receive differential signal pair C positive for 1000BASE-T physical layer connection via transformer.
8	TD_M_C	passive	Transmit/receive differential signal pair C negative for 1000BASE-T physical layer connection via transformer.
9	VDDA2P5	power_in	2.5V analog power supply with ±5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin.
10	TD_P_D	passive	Transmit/receive differential signal pair D positive for 1000BASE-T physical layer connection via transformer.
11	TD_M_D	passive	Transmit/receive differential signal pair D negative for 1000BASE-T physical layer connection via transformer.
12	RBIAS	passive	Bias resistor connection terminal; requires external 11kΩ ±1% resistor to ground for impedance network tuning.
13	VDDA1P8	power_in	1.8V analog power supply with ±5% tolerance; no external power required in dual-supply mode, but 1µF and 0.1µF capacitors to ground recommended if external supply used.
14	XO	output	Crystal oscillator output terminal for 25MHz crystal; keep floating if external clock source is used on XI pin.
15	XI	input	Crystal oscillator input terminal accepting 25MHz oscillator or crystal with 50ppm frequency accuracy and 1.5V to 1.9V amplitude.
16	MDC	input	Management data clock input synchronized to MDIO data; maximum clock rate is 25MHz with no minimum requirement.
17	MDIO	bidirectional	Bidirectional management data I/O terminal requiring external 1.5kΩ to 2.2kΩ pull-up resistor to VDDIO for IEEE 802.3 compliance.
18	CLK_OUT	output	Programmable clock output providing 25MHz, 125MHz, or divide-by-5 derived clock synchronized to XI, RX, or TX reference per IO_MUX_CFG register.
19	VDDIO	power_in	I/O power supply selectable as 3.3V (±5%), 2.5V (±5%), or 1.8V (±5%); requires 1µF and 0.1µF decoupling capacitors to ground on each pin.
20	JTAG_CLK	input	JTAG test clock input compliant with IEEE 1149.1 standard supporting maximum 2.5MHz clock frequency; requires internal pull-up resistor.
21	JTAG_TDO	output	JTAG test data output pin providing serial scan data from IEEE 1149.1 compliant test interface.
22	JTAG_TMS	input	JTAG test mode select input controlling TAP controller state machine per IEEE 1149.1; requires internal pull-up and recommended held high with 3 clock pulses for reset.
23	JTAG_TDI	input	JTAG test data input pin for serial scan input compliance with IEEE 1149.1 standard; requires internal pull-up resistor.
24	VDD1P0	power_in	1V analog power supply with +15.5% and -5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin.
25	TX_D3	input	RGMII transmit data bit 3 synchronized to GTX_CLK; transfers data from MAC to PHY in RGMII mode at 10/100/1000Mbps.
26	TX_D2	input	RGMII transmit data bit 2 synchronized to GTX_CLK; transfers data from MAC to PHY in RGMII mode at 10/100/1000Mbps.
27	TX_D1	input	RGMII transmit data bit 1 synchronized to GTX_CLK; transfers data from MAC to PHY in RGMII mode, or functions as SGMII_SIP differential pair in SGMII mode.
28	TX_D0	input	RGMII transmit data bit 0 synchronized to GTX_CLK; transfers data from MAC to PHY in RGMII mode, or functions as SGMII_SIN differential pair in SGMII mode.
29	GTX_CLK	input	RGMII transmit clock input from MAC with nominal 125MHz frequency for 1000Mbps; scaled to 25MHz at 100Mbps and 2.5MHz at 10Mbps operation.
30	VDDIO	power_in	I/O power supply selectable as 3.3V (±5%), 2.5V (±5%), or 1.8V (±5%); requires 1µF and 0.1µF decoupling capacitors to ground on each pin.
31	VDD1P0	power_in	1V analog power supply with +15.5% and -5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin.
32	RX_CLK	output	RGMII recovered receive clock output frequency dependent on link speed: 2.5MHz (10Mbps), 25MHz (100Mbps), or 125MHz (1000Mbps).
33	RX_D0	output	RGMII receive data bit 0 synchronized to RX_CLK; transfers data from PHY to MAC in RGMII mode, or functions as SGMII_COP differential pair in SGMII mode.
34	RX_D1	output	RGMII receive data bit 1 synchronized to RX_CLK; transfers data from PHY to MAC in RGMII mode, or functions as SGMII_CON differential pair in SGMII mode.
35	RX_D2	output	RGMII receive data bit 2 synchronized to RX_CLK; transfers data from PHY to MAC in RGMII mode, or functions as SGMII_SOP differential pair in SGMII mode.
36	RX_D3	output	RGMII receive data bit 3 synchronized to RX_CLK; transfers data from PHY to MAC in RGMII mode, or functions as SGMII_SON differential pair in SGMII mode.
37	TX_CTRL	input	RGMII transmit control combining GMII transmit enable and error signals using dual-edge clocking on GTX_CLK for 1000Mbps operation.
38	RX_CTRL	output	RGMII receive control combining receive data valid and error signals RXDV_ER using dual-edge clocking on RX_CLK; serves as configuration pin in Strap mode.
39	GPIO_0	output	Configurable general-purpose I/O providing multipurpose signal selection via GPIO_MUX_CTRL register; serves as RGMII RX clock delay configuration pin in Strap mode.
40	GPIO_1	output	Configurable general-purpose I/O providing multipurpose signal selection via GPIO_MUX_CTRL register; serves as RGMII clock delay configuration pins in Strap mode.
41	VDDIO	power_in	I/O power supply selectable as 3.3V (±5%), 2.5V (±5%), or 1.8V (±5%); requires 1µF and 0.1µF decoupling capacitors to ground on each pin.
42	VDD1P0	power_in	1V analog power supply with +15.5% and -5% tolerance; requires 1µF and 0.1µF decoupling capacitors to ground on each pin.
43	RESET_N	input	Active-low asynchronous reset input requiring minimum 1µs low pulse; initializes all internal registers to default state and relatches hardware configuration pins.
44	INT/PWDN	bidirectional	Dual-function open-drain output for interrupt signaling or active-low input for power-down mode; requires external 2.2kΩ pull-up to VDDIO when used as interrupt output.
45	LED_2	output	Configurable LED output pin providing activity or link status indication; default function shows transmit/receive activity with programmable LEDCR1 configuration.
46	LED_1	output	Configurable LED output pin providing link status indication; default function shows 1000BASE-T link establishment with programmable LEDCR1 configuration.
47	LED_0	output	Configurable LED output pin providing link establishment indication; default function shows active link status with programmable LEDCR1 configuration; serves as SGMII enable Strap pin.
48	VDDA1P8	power_in	1.8V analog power supply with ±5% tolerance; no external power required in dual-supply mode, but 1µF and 0.1µF capacitors to ground recommended if external supply used.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-48-EP(7x7)
Category	Interface
Pins	49

CAD (KiCad official)

Symbol: DP83867ERGZR
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: dp83867ergzr-etched.step / dp83867ergzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83867ergzr.step / dp83867ergzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (127 pp, sha256 101dd83b84e239fd, retrieved 2026-09-21, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF