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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83867CSRGZR

Texas Instruments · Ethernet Transceivers · VQFN-48-EP(7x7)

DP83867CSRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TD_P_A	passive	Differential media-side signal pair A, positive leg, connected through the external magnetics to the RJ-45 (MDI).
2	TD_M_A	passive	Differential media-side signal pair A, negative leg, connected through the external magnetics to the RJ-45 (MDI).
3	VDDA2P5	power_in	2.5 V analog supply, ±5% (2.375 V to 2.625 V); each pin needs 1 µF and 0.1 µF capacitors to GND.
4	TD_P_B	passive	Differential media-side signal pair B, positive leg (MDI).
5	TD_M_B	passive	Differential media-side signal pair B, negative leg (MDI).
6	VDD1P0	power_in	1 V analog supply, +15.5%/-5% (0.95 V to 1.155 V); each pin needs 1 µF and 0.1 µF capacitors to GND.
7	TD_P_C	passive	Differential media-side signal pair C, positive leg (MDI).
8	TD_M_C	passive	Differential media-side signal pair C, negative leg (MDI).
9	VDDA2P5	power_in	2.5 V analog supply, ±5% (2.375 V to 2.625 V); each pin needs 1 µF and 0.1 µF capacitors to GND.
10	TD_P_D	passive	Differential media-side signal pair D, positive leg (MDI).
11	TD_M_D	passive	Differential media-side signal pair D, negative leg (MDI).
12	RBIAS	passive	Bias resistor connection; connect an 11 kΩ ±1% resistor from this pin to GND.
13	VDDA1P8	power_in	1.8 V analog supply, ±5% (1.71 V to 1.89 V); no external supply is required and the pin must not be connected to any circuit when unused, while an external 1.8 V supply may optionally be connected with 1 µF and 0.1 µF capacitors.
14	XO	output	25 MHz crystal output (second terminal); must be left floating when a clock oscillator drives XI.
15	XI	input	25 MHz oscillator or crystal input (50 ppm); oscillator drive level is 1.5 to 1.9 Vpp.
16	MDC	input	Management data clock for MDIO, maximum 25 MHz with no minimum rate, and may be asynchronous to the MAC clocks.
17	MDIO	bidirectional	Management data I/O; requires an external pull-up of 1.5 kΩ per IEEE (2.2 kΩ acceptable).
18	CLK_OUT	output	Clock output; by default synchronized to the XI input clock and configurable through the IO_MUX_CFG register.
19	VDDIO	power_in	I/O supply, 1.8 V, 2.5 V or 3.3 V (±5%); each pin needs 1 µF and 0.1 µF capacitors to GND.
20	JTAG_CLK	input	IEEE 1149.1 JTAG test clock input with internal pull-up; maximum supported clock frequency is 2.5 MHz.
21	JTAG_TDO	output	IEEE 1149.1 JTAG test data output through which the latest test results are scanned out of the device.
22	JTAG_TMS	input	IEEE 1149.1 JTAG test mode select with internal pull-up; TI recommends holding it high and applying 3 clock cycles to reset JTAG.
23	JTAG_TDI	input	IEEE 1149.1 JTAG test data input with internal pull-up, through which test data is scanned into the device.
24	VDD1P0	power_in	1 V analog supply, +15.5%/-5% (0.95 V to 1.155 V); each pin needs 1 µF and 0.1 µF capacitors to GND.
25	TX_D3	input	RGMII transmit data bit 3 from MAC to PHY, synchronous to GTX_CLK, with internal pull-down.
26	TX_D2	input	RGMII transmit data bit 2 from MAC to PHY, synchronous to GTX_CLK, with internal pull-down.
27	TX_D1/SGMII_SIP	input	RGMII transmit data bit 1 in RGMII mode; positive SGMII differential data input in SGMII mode, which may be AC-coupled to the MAC with 0.1 µF.
28	TX_D0/SGMII_SIN	input	RGMII transmit data bit 0 in RGMII mode; negative SGMII differential data input in SGMII mode, which may be AC-coupled to the MAC with 0.1 µF.
29	GTX_CLK	input	RGMII transmit clock supplied continuously by the MAC; nominal frequency 125 MHz.
30	VDDIO	power_in	I/O supply, 1.8 V, 2.5 V or 3.3 V (±5%); each pin needs 1 µF and 0.1 µF capacitors to GND.
31	VDD1P0	power_in	1 V analog supply, +15.5%/-5% (0.95 V to 1.155 V); each pin needs 1 µF and 0.1 µF capacitors to GND.
32	RX_CLK	output	RGMII receive clock recovered from the line: 2.5 MHz at 10 Mbps, 25 MHz at 100 Mbps and 125 MHz at 1000 Mbps.
33	RX_D0/SGMII_COP	output	RGMII receive data bit 0 in RGMII mode; positive SGMII differential 625 MHz clock output in SGMII mode, which may be AC-coupled with 0.1 µF.
34	RX_D1/SGMII_CON	output	RGMII receive data bit 1 in RGMII mode; negative SGMII differential 625 MHz clock output in SGMII mode, which may be AC-coupled with 0.1 µF.
35	RX_D2/SGMII_SOP	output	RGMII receive data bit 2 in RGMII mode; positive SGMII differential data output in SGMII mode, which may be AC-coupled with 0.1 µF.
36	RX_D3/SGMII_SON	output	RGMII receive data bit 3 in RGMII mode; negative SGMII differential data output in SGMII mode, which may be AC-coupled with 0.1 µF.
37	TX_CTRL	input	RGMII transmit control carrying TX_EN and TX_ER encoded on both edges of GTX_CLK, with internal pull-down.
38	RX_CTRL	bidirectional	RGMII receive control carrying RXDV and RX_ER combined as RXDV_ER on both edges of RX_CLK; also a strap pin that must be configured to strap mode 3 or 4 (or bit 7 of register 0x0031 cleared).
39	GPIO_0	bidirectional	Multi-function general-purpose I/O configured through the GPIO_MUX_CTRL register; also a strap pin (modes 1 and 3 only).
40	GPIO_1	bidirectional	Multi-function general-purpose I/O configured through the GPIO_MUX_CTRL register; also a strap pin.
41	VDDIO	power_in	I/O supply, 1.8 V, 2.5 V or 3.3 V (±5%); each pin needs 1 µF and 0.1 µF capacitors to GND.
42	VDD1P0	power_in	1 V analog supply, +15.5%/-5% (0.95 V to 1.155 V); each pin needs 1 µF and 0.1 µF capacitors to GND.
43	RESET_N	input	Active-low reset with internal pull-up; must be held low for at least 1 µs to reinitialize the device and all registers.
44	INT/PWDN	bidirectional	Active-low power-down input by default; when configured as interrupt it is an open-drain output, and TI recommends a 2.2 kΩ external pull-up to VDDIO; internal pull-up.
45	LED_2	bidirectional	LED output and strap pin; by default indicates receive or transmit activity, with other functions set by LEDCR1[11:8].
46	LED_1	bidirectional	LED output and strap pin; by default indicates 1000BASE-T link established, with other functions set by LEDCR1[7:4].
47	LED_0	bidirectional	LED output and strap pin; by default indicates link established, with other functions set by LEDCR1[3:0].
48	VDDA1P8	power_in	1.8 V analog supply, ±5%; same rules as pin 13 (no external supply required, leave unconnected when unused, optional external 1.8 V with 1 µF and 0.1 µF capacitors).
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-48-EP(7x7)
Category	Interface
Pins	49

CAD (KiCad official)

Symbol: DP83867CSRGZR
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: dp83867csrgzr-etched.step / dp83867csrgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83867csrgzr.step / dp83867csrgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (127 pp, sha256 101dd83b84e239fd, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF