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DP83849IVSX
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Texas Instruments Ethernet Transceivers, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+116@@ -0,0 +1,116 @@+# DP83849IVSX++**Texas Instruments** · Ethernet Transceivers · TQFP-80(12x12)++DP83849IVSX from Texas Instruments, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CRS_A/CRS_DV_A | output | Asserted high in MII mode to indicate the receive medium is non-idle, or in RMII mode combines Carrier Sense and Receive Data Valid. |+| 2 | RX_ER_A/MDIX_EN_A | output | Asserted high synchronously to RX_CLK to indicate invalid symbol detection in 100Mb mode, or enables Auto-MDIX when strap pulled down. |+| 3 | COL_A | output | Asserted high to indicate detection of collision condition during simultaneous transmit and receive activity in half-duplex modes. |+| 4 | RXD0_A/PHYAD1 | output | Nibble-wide receive data signal driven synchronously to RX_CLK in MII mode, or carries PHY address bit 1 when sampled as strap during reset. |+| 5 | RXD1_A/PHYAD2 | output | Nibble-wide receive data signal driven synchronously to RX_CLK in MII mode, or carries PHY address bit 2 when sampled as strap during reset. |+| 6 | COREGND1 | power_in | Core ground connection requiring connection to system ground plane. |+| 7 | PFBIN1 | input | Power feedback input pin requiring 0.1µF capacitor connection to PFBOUT. |+| 8 | RXD2_A/CLK2MAC_DIS | output | Receive data signal in MII mode, or when strap pulled high disables CLK2MAC output. |+| 9 | RXD3_A/ED_EN_A | output | Receive data signal in MII mode, or when strap pulled high enables Energy Detect mode. |+| 10 | IOGND1 | power_in | I/O ground connection for I/O signal return path. |+| 11 | IOVDD1 | power_in | I/O 3.3V supply requiring 0.1µF bypass capacitor placed close to pin. |+| 12 | TX_CLK_A | output | 25MHz transmit clock output in 100Mb/s mode or 2.5MHz in 10Mb/s mode derived from 25MHz reference clock. |+| 13 | TX_EN_A | input | Active high input indicating presence of valid data on TXD[3:0] transmit data bus. |+| 14 | TXD0_A | input | Transmit data input sampled synchronously to TX_CLK in MII mode accepting 2.5-25MHz data. |+| 15 | TXD1_A | input | Transmit data input sampled synchronously to TX_CLK in MII mode accepting 2.5-25MHz data. |+| 16 | TXD2_A | input | Transmit data input sampled synchronously to TX_CLK in MII mode accepting 2.5-25MHz data. |+| 17 | TXD3_A/SNI_MODE_A | input | Transmit data input in MII mode, or when strap pulled high enables 10Mb/s SNI serial mode. |+| 18 | PWRDOWN_INT_A | input | Active low input for power down control, or when INT_OE bit set becomes open-drain interrupt output. |+| 19 | LED_LINK_A/AN0_A | output | LED output indicating link status in mode 1 or link with activity in modes 2-3, or carries auto-negotiation strap bit 0. |+| 20 | LED_SPEED_A/AN1_A | output | LED output on for 100Mb/s operation, off for 10Mb/s operation, or carries auto-negotiation strap bit 1. |+| 21 | LED_ACT/LED_COL/AN_EN_A | output | LED output for activity/collision/duplex indication depending on mode, or carries auto-negotiation enable strap. |+| 22 | ANAGND1 | power_in | Analog ground connection for analog signal return path. |+| 23 | TPRDM_A | bidirectional | 10BASE-T/100BASE-TX differential receive data pair negative; in Auto-MDIX mode can serve as transmit output pair. |+| 24 | TPRDP_A | bidirectional | 10BASE-T/100BASE-TX differential receive data pair positive; in Auto-MDIX mode can serve as transmit output pair. |+| 25 | CDGND1 | power_in | Common driver ground connection for differential pair biasing. |+| 26 | TPTDM_A | bidirectional | 10BASE-T/100BASE-TX differential transmit data pair negative; in Auto-MDIX mode can serve as receive input pair. |+| 27 | TPTDP_A | bidirectional | 10BASE-T/100BASE-TX differential transmit data pair positive; in Auto-MDIX mode can serve as receive input pair. |+| 28 | PFBIN2 | input | Power feedback input pin requiring 0.1µF capacitor connection to PFBOUT. |+| 29 | ANAGND2 | power_in | Analog ground connection for analog signal return path. |+| 30 | ANA33VDD | power_in | Analog 3.3V supply requiring connection to analog power rail. |+| 31 | PFBOUT | output | Power feedback output requiring 10µF and 0.1µF capacitors for connection to PFBIN pins. |+| 32 | RBIAS | input | Bias resistor connection requiring 4-87kΩ 1% resistor to ground for receiver biasing. |+| 33 | ANAGND3 | power_in | Analog ground connection for analog signal return path. |+| 34 | PFBIN3 | input | Power feedback input pin requiring 0.1µF capacitor connection to PFBOUT. |+| 35 | TPTDP_B | bidirectional | 10BASE-T/100BASE-TX differential transmit data pair positive for Port B; in Auto-MDIX mode can serve as receive input. |+| 36 | TPTDM_B | bidirectional | 10BASE-T/100BASE-TX differential transmit data pair negative for Port B; in Auto-MDIX mode can serve as receive input. |+| 37 | CDGND2 | power_in | Common driver ground connection for differential pair biasing. |+| 38 | TPRDP_B | bidirectional | 10BASE-T/100BASE-TX differential receive data pair positive for Port B; in Auto-MDIX mode can serve as transmit output. |+| 39 | TPRDM_B | bidirectional | 10BASE-T/100BASE-TX differential receive data pair negative for Port B; in Auto-MDIX mode can serve as transmit output. |+| 40 | ANAGND4 | power_in | Analog ground connection for analog signal return path. |+| 41 | LED_ACT/LED_COL/AN_EN_B | output | LED output for Port B activity/collision/duplex indication, or carries auto-negotiation enable strap for Port B. |+| 42 | LED_SPEED_B/AN1_B | output | LED output on for 100Mb/s operation, off for 10Mb/s for Port B, or carries auto-negotiation strap bit 1. |+| 43 | LED_LINK_B/AN0_B | output | LED output indicating link status for Port B, or carries auto-negotiation strap bit 0. |+| 44 | PWRDOWN_INT_B | input | Active low input for Port B power down control, or when INT_OE bit set becomes open-drain interrupt output. |+| 45 | TXD3_B/SNI_MODE_B | input | Transmit data input for Port B, or when strap pulled high enables 10Mb/s SNI serial mode. |+| 46 | TXD2_B | input | Transmit data input sampled synchronously to TX_CLK in MII mode for Port B. |+| 47 | TXD1_B | input | Transmit data input sampled synchronously to TX_CLK in MII mode for Port B. |+| 48 | TXD0_B | input | Transmit data input sampled synchronously to TX_CLK in MII mode for Port B. |+| 49 | TX_EN_B | input | Active high input indicating presence of valid data on TXD[3:0] transmit bus for Port B. |+| 50 | TX_CLK_B | output | 25MHz transmit clock output in 100Mb/s mode or 2.5MHz in 10Mb/s mode for Port B. |+| 51 | IOVDD2 | power_in | I/O 3.3V supply requiring 0.1µF bypass capacitor placed close to pin. |+| 52 | IOGND2 | power_in | I/O ground connection for I/O signal return path. |+| 53 | RXD3_B/ED_EN_B | output | Receive data signal in MII mode for Port B, or when strap pulled high enables Energy Detect mode. |+| 54 | PFBIN4 | input | Power feedback input pin requiring 0.1µF capacitor connection to PFBOUT. |+| 55 | COREGND2 | power_in | Core ground connection requiring connection to system ground plane. |+| 56 | RXD2_B/EXTENDER_EN | output | Receive data signal in MII mode for Port B, or when strap pulled high enables extender mode for range extension. |+| 57 | RXD1_B/PHYAD4 | output | Receive data signal for Port B in MII mode, or carries PHY address bit 4 when sampled as strap during reset. |+| 58 | RXD0_B/PHYAD3 | output | Receive data signal for Port B in MII mode, or carries PHY address bit 3 when sampled as strap during reset. |+| 59 | COL_B | output | Asserted high to indicate collision detection during simultaneous transmit and receive for Port B half-duplex. |+| 60 | RX_ER_B/MDIX_EN_B | output | Invalid symbol detection output for Port B, or when strap pulled down disables Auto-MDIX for Port B. |+| 61 | CRS_B/CRS_DV_B/LED_CFG_B | output | Carrier Sense output for Port B indicating receive medium activity, or carries LED configuration strap. |+| 62 | RX_DV_B/MII_MODE_B | output | Receive data valid indicator for Port B, or when strap pulled high enables RMII or SNI mode. |+| 63 | RX_CLK_B | output | Recovered receive clock for Port B at 25MHz in 100Mb/s mode or 2.5MHz in 10Mb/s mode. |+| 64 | IOGND3 | power_in | I/O ground connection for I/O signal return path. |+| 65 | IOVDD3 | power_in | I/O 3.3V supply requiring 0.1µF bypass capacitor placed close to pin. |+| 66 | MDIO | bidirectional | Bi-directional management data I/O for serial management interface requiring 1.5kΩ pullup resistor. |+| 67 | MDC | input | Management data clock input for serial management interface with maximum 25MHz clock rate. |+| 68 | CLK2MAC | output | Clock output at 25MHz in MII mode or 50MHz in RMII mode that can be disabled via CLK2MAC_DIS strap. |+| 69 | X2 | output | Crystal oscillator output for connection to external 25MHz crystal resonator, leave unconnected if using external CMOS oscillator. |+| 70 | X1 | input | Primary clock reference input requiring 25MHz ±50ppm clock source for MII mode or 50MHz for RMII mode. |+| 71 | RESET_N | input | Active low hardware reset input requiring minimum 1µs pulse to reinitialize device and re-latch hardware configuration pins. |+| 72 | TCK | input | JTAG test clock input with weak internal pullup for boundary scan testing. |+| 73 | TDO | output | JTAG test data output for boundary scan chain communication. |+| 74 | TMS | input | JTAG test mode select input with weak internal pullup for test state machine control. |+| 75 | TRSTN | input | JTAG test reset active low input with weak internal pullup to reset test scan chain. |+| 76 | TDI | input | JTAG test data input with weak internal pullup for boundary scan data injection. |+| 77 | IOGND4 | power_in | I/O ground connection for I/O signal return path. |+| 78 | IOVDD4 | power_in | I/O 3.3V supply requiring 0.1µF bypass capacitor placed close to pin. |+| 79 | RX_CLK_A | output | Recovered receive clock for Port A at 25MHz in 100Mb/s mode or 2.5MHz in 10Mb/s mode. |+| 80 | RX_DV_A/MII_MODE_A | output | Receive data valid indicator for Port A, or when strap pulled high enables RMII or SNI mode. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-80(12x12) |+| Category | Interface |+| Pins | 80 |++## CAD (KiCad official)++- Symbol: `DP83849IVSX`+- Footprint: `Package_QFP:TQFP-80_12x12mm_P0.5mm`+- 3D model: TQFP-80(12x12) (KiCad packages3D, STEP)+- 3D model files: `dp83849ivsx-etched.step` / `dp83849ivsx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83849ivsx.step` / `dp83849ivsx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83849i) (106 pp, sha256 `cda2b378740678e3`, retrieved 2026-09-24, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dp83849ivsx-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "dp83849ivsx",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dp83849ivsx.kicad_sym",+ "dp83849ivsx.kicad_mod",+ "dp83849ivsx.glb",+ "dp83849ivsx.step",+ "dp83849ivsx.lbr",+ "docs/hero.png",+ "docs/dp83849ivsx-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DP83849IVSX",+ "manufacturer": "Texas Instruments",+ "package": "TQFP-80(12x12)",+ "pin_count": 80,+ "category": "Interface",+ "subcategory": "Ethernet Transceivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dp83849i",+ "parts": {+ "symbol": "dp83849ivsx.kicad_sym",+ "footprint": "dp83849ivsx.kicad_mod",+ "model_3d": "dp83849ivsx-etched.glb",+ "model_3d_plain": "dp83849ivsx.glb",+ "model_3d_step": "dp83849ivsx-etched.step",+ "model_3d_step_plain": "dp83849ivsx.step",+ "lbr": "dp83849ivsx.lbr"+ },+ "distributor_links": {+ "lcsc": "C2671040"+ },+ "pins": [+ {+ "number": "1",+ "name": "CRS_A/CRS_DV_A",+ "type": "output",+ "description": "Asserted high in MII mode to indicate the receive medium is non-idle, or in RMII mode combines Carrier Sense and Receive Data Valid."+ },+ {+ "number": "2",+ "name": "RX_ER_A/MDIX_EN_A",+ "type": "output",+ "description": "Asserted high synchronously to RX_CLK to indicate invalid symbol detection in 100Mb mode, or enables Auto-MDIX when strap pulled down."+ },+ {+ "number": "3",+ "name": "COL_A",+ "type": "output",+ "description": "Asserted high to indicate detection of collision condition during simultaneous transmit and receive activity in half-duplex modes."+ },+ {+ "number": "4",+ "name": "RXD0_A/PHYAD1",+ "type": "output",+ "description": "Nibble-wide receive data signal driven synchronously to RX_CLK in MII mode, or carries PHY address bit 1 when sampled as strap during reset."+ },+ {+ "number": "5",+ "name": "RXD1_A/PHYAD2",+ "type": "output",+ "description": "Nibble-wide receive data signal driven synchronously to RX_CLK in MII mode, or carries PHY address bit 2 when sampled as strap during reset."+ },+ {+ "number": "6",+ "name": "COREGND1",+ "type": "power_in",+ "description": "Core ground connection requiring connection to system ground plane."+ },+ {+ "number": "7",+ "name": "PFBIN1",+ "type": "input",+ "description": "Power feedback input pin requiring 0.1µF capacitor connection to PFBOUT."+ },+ {+ "number": "8",+ "name": "RXD2_A/CLK2MAC_DIS",+ "type": "output",+ "description": "Receive data signal in MII mode, or when strap pulled high disables CLK2MAC output."+ },+ {+ "number": "9",+ "name": "RXD3_A/ED_EN_A",+ "type": "output",+ "description": "Receive data signal in MII mode, or when strap pulled high enables Energy Detect mode."+ },+ {+ "number": "10",+ "name": "IOGND1",+ "type": "power_in",+ "description": "I/O ground connection for I/O signal return path."+ },+ {+ "number": "11",+ "name": "IOVDD1",+ "type": "power_in",+ "description": "I/O 3.3V supply requiring 0.1µF bypass capacitor placed close to pin."+ },+ {+ "number": "12",+ "name": "TX_CLK_A",+ "type": "output",+ "description": "25MHz transmit clock output in 100Mb/s mode or 2.5MHz in 10Mb/s mode derived from 25MHz reference clock."+ },+ {+ "number": "13",+ "name": "TX_EN_A",+ "type": "input",+ "description": "Active high input indicating presence of valid data on TXD[3:0] transmit data bus."+ },+ {+ "number": "14",+ "name": "TXD0_A",+ "type": "input",+ "description": "Transmit data input sampled synchronously to TX_CLK in MII mode accepting 2.5-25MHz data."+ },+ {+ "number": "15",+ "name": "TXD1_A",+ "type": "input",+ "description": "Transmit data input sampled synchronously to TX_CLK in MII mode accepting 2.5-25MHz data."+ },+ {+ "number": "16",+ "name": "TXD2_A",+ "type": "input",+ "description": "Transmit data input sampled synchronously to TX_CLK in MII mode accepting 2.5-25MHz data."+ },+ {+ "number": "17",+ "name": "TXD3_A/SNI_MODE_A",+ "type": "input",+ "description": "Transmit data input in MII mode, or when strap pulled high enables 10Mb/s SNI serial mode."+ },+ {+ "number": "18",+ "name": "PWRDOWN_INT_A",+ "type": "input",+ "description": "Active low input for power down control, or when INT_OE bit set becomes open-drain interrupt output."+ },+ {+ "number": "19",+ "name": "LED_LINK_A/AN0_A",+ "type": "output",+ "description": "LED output indicating link status in mode 1 or link with activity in modes 2-3, or carries auto-negotiation strap bit 0."+ },+ {+ "number": "20",+ "name": "LED_SPEED_A/AN1_A",+ "type": "output",+ "description": "LED output on for 100Mb/s operation, off for 10Mb/s operation, or carries auto-negotiation strap bit 1."+ },+ {+ "number": "21",+ "name": "LED_ACT/LED_COL/AN_EN_A",+ "type": "output",+ "description": "LED output for activity/collision/duplex indication depending on mode, or carries auto-negotiation enable strap."+ },+ {+ "number": "22",+ "name": "ANAGND1",+ "type": "power_in",+ "description": "Analog ground connection for analog signal return path."+ },+ {+ "number": "23",+ "name": "TPRDM_A",+ "type": "bidirectional",+ "description": "10BASE-T/100BASE-TX differential receive data pair negative; in Auto-MDIX mode can serve as transmit output pair."+ },+ {+ "number": "24",+ "name": "TPRDP_A",+ "type": "bidirectional",+ "description": "10BASE-T/100BASE-TX differential receive data pair positive; in Auto-MDIX mode can serve as transmit output pair."+ },+ {+ "number": "25",+ "name": "CDGND1",+ "type": "power_in",+ "description": "Common driver ground connection for differential pair biasing."+ },+ {+ "number": "26",+ "name": "TPTDM_A",+ "type": "bidirectional",+ "description": "10BASE-T/100BASE-TX differential transmit data pair negative; in Auto-MDIX mode can serve as receive input pair."+ },+ {+ "number": "27",+ "name": "TPTDP_A",+ "type": "bidirectional",+ "description": "10BASE-T/100BASE-TX differential transmit data pair positive; in Auto-MDIX mode can serve as receive input pair."+ },+ {+ "number": "28",+ "name": "PFBIN2",+ "type": "input",+ "description": "Power feedback input pin requiring 0.1µF capacitor connection to PFBOUT."+ },+ {+ "number": "29",+ "name": "ANAGND2",+ "type": "power_in",+ "description": "Analog ground connection for analog signal return path."+ },+ {+ "number": "30",+ "name": "ANA33VDD",+ "type": "power_in",+ "description": "Analog 3.3V supply requiring connection to analog power rail."+ },+ {+ "number": "31",+ "name": "PFBOUT",+ "type": "output",+ "description": "Power feedback output requiring 10µF and 0.1µF capacitors for connection to PFBIN pins."+ },+ {+ "number": "32",+ "name": "RBIAS",+ "type": "input",+ "description": "Bias resistor connection requiring 4-87kΩ 1% resistor to ground for receiver biasing."+ },+ {+ "number": "33",+ "name": "ANAGND3",+ "type": "power_in",+ "description": "Analog ground connection for analog signal return path."+ },+ {+ "number": "34",+ "name": "PFBIN3",+ "type": "input",+ "description": "Power feedback input pin requiring 0.1µF capacitor connection to PFBOUT."+ },+ {+ "number": "35",+ "name": "TPTDP_B",+ "type": "bidirectional",+ "description": "10BASE-T/100BASE-TX differential transmit data pair positive for Port B; in Auto-MDIX mode can serve as receive input."+ },+ {+ "number": "36",+ "name": "TPTDM_B",+ "type": "bidirectional",+ "description": "10BASE-T/100BASE-TX differential transmit data pair negative for Port B; in Auto-MDIX mode can serve as receive input."+ },+ {+ "number": "37",+ "name": "CDGND2",+ "type": "power_in",+ "description": "Common driver ground connection for differential pair biasing."+ },+ {+ "number": "38",+ "name": "TPRDP_B",+ "type": "bidirectional",+ "description": "10BASE-T/100BASE-TX differential receive data pair positive for Port B; in Auto-MDIX mode can serve as transmit output."+ },+ {+ "number": "39",+ "name": "TPRDM_B",+ "type": "bidirectional",+ "description": "10BASE-T/100BASE-TX differential receive data pair negative for Port B; in Auto-MDIX mode can serve as transmit output."+ },+ {+ "number": "40",+ "name": "ANAGND4",+ "type": "power_in",+ "description": "Analog ground connection for analog signal return path."+ },+ {+ "number": "41",+ "name": "LED_ACT/LED_COL/AN_EN_B",+ "type": "output",+ "description": "LED output for Port B activity/collision/duplex indication, or carries auto-negotiation enable strap for Port B."+ },+ {+ "number": "42",+ "name": "LED_SPEED_B/AN1_B",+ "type": "output",+ "description": "LED output on for 100Mb/s operation, off for 10Mb/s for Port B, or carries auto-negotiation strap bit 1."+ },+ {+ "number": "43",+ "name": "LED_LINK_B/AN0_B",+ "type": "output",+ "description": "LED output indicating link status for Port B, or carries auto-negotiation strap bit 0."+ },+ {+ "number": "44",+ "name": "PWRDOWN_INT_B",+ "type": "input",+ "description": "Active low input for Port B power down control, or when INT_OE bit set becomes open-drain interrupt output."+ },+ {+ "number": "45",+ "name": "TXD3_B/SNI_MODE_B",+ "type": "input",+ "description": "Transmit data input for Port B, or when strap pulled high enables 10Mb/s SNI serial mode."+ },+ {+ "number": "46",+ "name": "TXD2_B",+ "type": "input",+ "description": "Transmit data input sampled synchronously to TX_CLK in MII mode for Port B."+ },+ {+ "number": "47",+ "name": "TXD1_B",+ "type": "input",+ "description": "Transmit data input sampled synchronously to TX_CLK in MII mode for Port B."+ },+ {+ "number": "48",+ "name": "TXD0_B",+ "type": "input",+ "description": "Transmit data input sampled synchronously to TX_CLK in MII mode for Port B."+ },+ {+ "number": "49",+ "name": "TX_EN_B",+ "type": "input",+ "description": "Active high input indicating presence of valid data on TXD[3:0] transmit bus for Port B."+ },+ {+ "number": "50",+ "name": "TX_CLK_B",+ "type": "output",+ "description": "25MHz transmit clock output in 100Mb/s mode or 2.5MHz in 10Mb/s mode for Port B."+ },+ {+ "number": "51",+ "name": "IOVDD2",+ "type": "power_in",+ "description": "I/O 3.3V supply requiring 0.1µF bypass capacitor placed close to pin."+ },+ {+ "number": "52",+ "name": "IOGND2",+ "type": "power_in",+ "description": "I/O ground connection for I/O signal return path."+ },+ {+ "number": "53",+ "name": "RXD3_B/ED_EN_B",+ "type": "output",+ "description": "Receive data signal in MII mode for Port B, or when strap pulled high enables Energy Detect mode."+ },+ {+ "number": "54",+ "name": "PFBIN4",+ "type": "input",+ "description": "Power feedback input pin requiring 0.1µF capacitor connection to PFBOUT."+ },+ {+ "number": "55",+ "name": "COREGND2",+ "type": "power_in",+ "description": "Core ground connection requiring connection to system ground plane."+ },+ {+ "number": "56",+ "name": "RXD2_B/EXTENDER_EN",+ "type": "output",+ "description": "Receive data signal in MII mode for Port B, or when strap pulled high enables extender mode for range extension."+ },+ {+ "number": "57",+ "name": "RXD1_B/PHYAD4",+ "type": "output",+ "description": "Receive data signal for Port B in MII mode, or carries PHY address bit 4 when sampled as strap during reset."+ },+ {+ "number": "58",+ "name": "RXD0_B/PHYAD3",+ "type": "output",+ "description": "Receive data signal for Port B in MII mode, or carries PHY address bit 3 when sampled as strap during reset."+ },+ {+ "number": "59",+ "name": "COL_B",+ "type": "output",+ "description": "Asserted high to indicate collision detection during simultaneous transmit and receive for Port B half-duplex."+ },+ {+ "number": "60",+ "name": "RX_ER_B/MDIX_EN_B",+ "type": "output",+ "description": "Invalid symbol detection output for Port B, or when strap pulled down disables Auto-MDIX for Port B."+ },+ {+ "number": "61",+ "name": "CRS_B/CRS_DV_B/LED_CFG_B",+ "type": "output",+ "description": "Carrier Sense output for Port B indicating receive medium activity, or carries LED configuration strap."+ },+ {+ "number": "62",+ "name": "RX_DV_B/MII_MODE_B",+ "type": "output",+ "description": "Receive data valid indicator for Port B, or when strap pulled high enables RMII or SNI mode."+ },+ {+ "number": "63",+ "name": "RX_CLK_B",+ "type": "output",+ "description": "Recovered receive clock for Port B at 25MHz in 100Mb/s mode or 2.5MHz in 10Mb/s mode."+ },+ {+ "number": "64",+ "name": "IOGND3",+ "type": "power_in",+ "description": "I/O ground connection for I/O signal return path."+ },+ {+ "number": "65",+ "name": "IOVDD3",+ "type": "power_in",+ "description": "I/O 3.3V supply requiring 0.1µF bypass capacitor placed close to pin."+ },+ {+ "number": "66",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Bi-directional management data I/O for serial management interface requiring 1.5kΩ pullup resistor."+ },+ {+ "number": "67",+ "name": "MDC",+ "type": "input",+ "description": "Management data clock input for serial management interface with maximum 25MHz clock rate."+ },+ {+ "number": "68",+ "name": "CLK2MAC",+ "type": "output",+ "description": "Clock output at 25MHz in MII mode or 50MHz in RMII mode that can be disabled via CLK2MAC_DIS strap."+ },+ {+ "number": "69",+ "name": "X2",+ "type": "output",+ "description": "Crystal oscillator output for connection to external 25MHz crystal resonator, leave unconnected if using external CMOS oscillator."+ },+ {+ "number": "70",+ "name": "X1",+ "type": "input",+ "description": "Primary clock reference input requiring 25MHz ±50ppm clock source for MII mode or 50MHz for RMII mode."+ },+ {+ "number": "71",+ "name": "RESET_N",+ "type": "input",+ "description": "Active low hardware reset input requiring minimum 1µs pulse to reinitialize device and re-latch hardware configuration pins."+ },+ {+ "number": "72",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock input with weak internal pullup for boundary scan testing."+ },+ {+ "number": "73",+ "name": "TDO",+ "type": "output",+ "description": "JTAG test data output for boundary scan chain communication."+ },+ {+ "number": "74",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test mode select input with weak internal pullup for test state machine control."+ },+ {+ "number": "75",+ "name": "TRSTN",+ "type": "input",+ "description": "JTAG test reset active low input with weak internal pullup to reset test scan chain."+ },+ {+ "number": "76",+ "name": "TDI",+ "type": "input",+ "description": "JTAG test data input with weak internal pullup for boundary scan data injection."+ },+ {+ "number": "77",+ "name": "IOGND4",+ "type": "power_in",+ "description": "I/O ground connection for I/O signal return path."+ },+ {+ "number": "78",+ "name": "IOVDD4",+ "type": "power_in",+ "description": "I/O 3.3V supply requiring 0.1µF bypass capacitor placed close to pin."+ },+ {+ "number": "79",+ "name": "RX_CLK_A",+ "type": "output",+ "description": "Recovered receive clock for Port A at 25MHz in 100Mb/s mode or 2.5MHz in 10Mb/s mode."+ },+ {+ "number": "80",+ "name": "RX_DV_A/MII_MODE_A",+ "type": "output",+ "description": "Receive data valid indicator for Port A, or when strap pulled high enables RMII or SNI mode."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Dual-purpose pins with strap functions classified by primary functional mode after reset latch-in; c"+ ],+ "pages_sent": 106,+ "cost_usd": 1.2368,+ "at": "2026-09-24T01:10:37"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dp83849i",+ "pages": 106,+ "sha256": "cda2b378740678e3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 80,+ "described": 80,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}