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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83849IVSX

Texas Instruments · Ethernet Transceivers · TQFP-80(12x12)

DP83849IVSX from Texas Instruments, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CRS_A/CRS_DV_A	output	Asserted high in MII mode to indicate the receive medium is non-idle, or in RMII mode combines Carrier Sense and Receive Data Valid.
2	RX_ER_A/MDIX_EN_A	output	Asserted high synchronously to RX_CLK to indicate invalid symbol detection in 100Mb mode, or enables Auto-MDIX when strap pulled down.
3	COL_A	output	Asserted high to indicate detection of collision condition during simultaneous transmit and receive activity in half-duplex modes.
4	RXD0_A/PHYAD1	output	Nibble-wide receive data signal driven synchronously to RX_CLK in MII mode, or carries PHY address bit 1 when sampled as strap during reset.
5	RXD1_A/PHYAD2	output	Nibble-wide receive data signal driven synchronously to RX_CLK in MII mode, or carries PHY address bit 2 when sampled as strap during reset.
6	COREGND1	power_in	Core ground connection requiring connection to system ground plane.
7	PFBIN1	input	Power feedback input pin requiring 0.1µF capacitor connection to PFBOUT.
8	RXD2_A/CLK2MAC_DIS	output	Receive data signal in MII mode, or when strap pulled high disables CLK2MAC output.
9	RXD3_A/ED_EN_A	output	Receive data signal in MII mode, or when strap pulled high enables Energy Detect mode.
10	IOGND1	power_in	I/O ground connection for I/O signal return path.
11	IOVDD1	power_in	I/O 3.3V supply requiring 0.1µF bypass capacitor placed close to pin.
12	TX_CLK_A	output	25MHz transmit clock output in 100Mb/s mode or 2.5MHz in 10Mb/s mode derived from 25MHz reference clock.
13	TX_EN_A	input	Active high input indicating presence of valid data on TXD[3:0] transmit data bus.
14	TXD0_A	input	Transmit data input sampled synchronously to TX_CLK in MII mode accepting 2.5-25MHz data.
15	TXD1_A	input	Transmit data input sampled synchronously to TX_CLK in MII mode accepting 2.5-25MHz data.
16	TXD2_A	input	Transmit data input sampled synchronously to TX_CLK in MII mode accepting 2.5-25MHz data.
17	TXD3_A/SNI_MODE_A	input	Transmit data input in MII mode, or when strap pulled high enables 10Mb/s SNI serial mode.
18	PWRDOWN_INT_A	input	Active low input for power down control, or when INT_OE bit set becomes open-drain interrupt output.
19	LED_LINK_A/AN0_A	output	LED output indicating link status in mode 1 or link with activity in modes 2-3, or carries auto-negotiation strap bit 0.
20	LED_SPEED_A/AN1_A	output	LED output on for 100Mb/s operation, off for 10Mb/s operation, or carries auto-negotiation strap bit 1.
21	LED_ACT/LED_COL/AN_EN_A	output	LED output for activity/collision/duplex indication depending on mode, or carries auto-negotiation enable strap.
22	ANAGND1	power_in	Analog ground connection for analog signal return path.
23	TPRDM_A	bidirectional	10BASE-T/100BASE-TX differential receive data pair negative; in Auto-MDIX mode can serve as transmit output pair.
24	TPRDP_A	bidirectional	10BASE-T/100BASE-TX differential receive data pair positive; in Auto-MDIX mode can serve as transmit output pair.
25	CDGND1	power_in	Common driver ground connection for differential pair biasing.
26	TPTDM_A	bidirectional	10BASE-T/100BASE-TX differential transmit data pair negative; in Auto-MDIX mode can serve as receive input pair.
27	TPTDP_A	bidirectional	10BASE-T/100BASE-TX differential transmit data pair positive; in Auto-MDIX mode can serve as receive input pair.
28	PFBIN2	input	Power feedback input pin requiring 0.1µF capacitor connection to PFBOUT.
29	ANAGND2	power_in	Analog ground connection for analog signal return path.
30	ANA33VDD	power_in	Analog 3.3V supply requiring connection to analog power rail.
31	PFBOUT	output	Power feedback output requiring 10µF and 0.1µF capacitors for connection to PFBIN pins.
32	RBIAS	input	Bias resistor connection requiring 4-87kΩ 1% resistor to ground for receiver biasing.
33	ANAGND3	power_in	Analog ground connection for analog signal return path.
34	PFBIN3	input	Power feedback input pin requiring 0.1µF capacitor connection to PFBOUT.
35	TPTDP_B	bidirectional	10BASE-T/100BASE-TX differential transmit data pair positive for Port B; in Auto-MDIX mode can serve as receive input.
36	TPTDM_B	bidirectional	10BASE-T/100BASE-TX differential transmit data pair negative for Port B; in Auto-MDIX mode can serve as receive input.
37	CDGND2	power_in	Common driver ground connection for differential pair biasing.
38	TPRDP_B	bidirectional	10BASE-T/100BASE-TX differential receive data pair positive for Port B; in Auto-MDIX mode can serve as transmit output.
39	TPRDM_B	bidirectional	10BASE-T/100BASE-TX differential receive data pair negative for Port B; in Auto-MDIX mode can serve as transmit output.
40	ANAGND4	power_in	Analog ground connection for analog signal return path.
41	LED_ACT/LED_COL/AN_EN_B	output	LED output for Port B activity/collision/duplex indication, or carries auto-negotiation enable strap for Port B.
42	LED_SPEED_B/AN1_B	output	LED output on for 100Mb/s operation, off for 10Mb/s for Port B, or carries auto-negotiation strap bit 1.
43	LED_LINK_B/AN0_B	output	LED output indicating link status for Port B, or carries auto-negotiation strap bit 0.
44	PWRDOWN_INT_B	input	Active low input for Port B power down control, or when INT_OE bit set becomes open-drain interrupt output.
45	TXD3_B/SNI_MODE_B	input	Transmit data input for Port B, or when strap pulled high enables 10Mb/s SNI serial mode.
46	TXD2_B	input	Transmit data input sampled synchronously to TX_CLK in MII mode for Port B.
47	TXD1_B	input	Transmit data input sampled synchronously to TX_CLK in MII mode for Port B.
48	TXD0_B	input	Transmit data input sampled synchronously to TX_CLK in MII mode for Port B.
49	TX_EN_B	input	Active high input indicating presence of valid data on TXD[3:0] transmit bus for Port B.
50	TX_CLK_B	output	25MHz transmit clock output in 100Mb/s mode or 2.5MHz in 10Mb/s mode for Port B.
51	IOVDD2	power_in	I/O 3.3V supply requiring 0.1µF bypass capacitor placed close to pin.
52	IOGND2	power_in	I/O ground connection for I/O signal return path.
53	RXD3_B/ED_EN_B	output	Receive data signal in MII mode for Port B, or when strap pulled high enables Energy Detect mode.
54	PFBIN4	input	Power feedback input pin requiring 0.1µF capacitor connection to PFBOUT.
55	COREGND2	power_in	Core ground connection requiring connection to system ground plane.
56	RXD2_B/EXTENDER_EN	output	Receive data signal in MII mode for Port B, or when strap pulled high enables extender mode for range extension.
57	RXD1_B/PHYAD4	output	Receive data signal for Port B in MII mode, or carries PHY address bit 4 when sampled as strap during reset.
58	RXD0_B/PHYAD3	output	Receive data signal for Port B in MII mode, or carries PHY address bit 3 when sampled as strap during reset.
59	COL_B	output	Asserted high to indicate collision detection during simultaneous transmit and receive for Port B half-duplex.
60	RX_ER_B/MDIX_EN_B	output	Invalid symbol detection output for Port B, or when strap pulled down disables Auto-MDIX for Port B.
61	CRS_B/CRS_DV_B/LED_CFG_B	output	Carrier Sense output for Port B indicating receive medium activity, or carries LED configuration strap.
62	RX_DV_B/MII_MODE_B	output	Receive data valid indicator for Port B, or when strap pulled high enables RMII or SNI mode.
63	RX_CLK_B	output	Recovered receive clock for Port B at 25MHz in 100Mb/s mode or 2.5MHz in 10Mb/s mode.
64	IOGND3	power_in	I/O ground connection for I/O signal return path.
65	IOVDD3	power_in	I/O 3.3V supply requiring 0.1µF bypass capacitor placed close to pin.
66	MDIO	bidirectional	Bi-directional management data I/O for serial management interface requiring 1.5kΩ pullup resistor.
67	MDC	input	Management data clock input for serial management interface with maximum 25MHz clock rate.
68	CLK2MAC	output	Clock output at 25MHz in MII mode or 50MHz in RMII mode that can be disabled via CLK2MAC_DIS strap.
69	X2	output	Crystal oscillator output for connection to external 25MHz crystal resonator, leave unconnected if using external CMOS oscillator.
70	X1	input	Primary clock reference input requiring 25MHz ±50ppm clock source for MII mode or 50MHz for RMII mode.
71	RESET_N	input	Active low hardware reset input requiring minimum 1µs pulse to reinitialize device and re-latch hardware configuration pins.
72	TCK	input	JTAG test clock input with weak internal pullup for boundary scan testing.
73	TDO	output	JTAG test data output for boundary scan chain communication.
74	TMS	input	JTAG test mode select input with weak internal pullup for test state machine control.
75	TRSTN	input	JTAG test reset active low input with weak internal pullup to reset test scan chain.
76	TDI	input	JTAG test data input with weak internal pullup for boundary scan data injection.
77	IOGND4	power_in	I/O ground connection for I/O signal return path.
78	IOVDD4	power_in	I/O 3.3V supply requiring 0.1µF bypass capacitor placed close to pin.
79	RX_CLK_A	output	Recovered receive clock for Port A at 25MHz in 100Mb/s mode or 2.5MHz in 10Mb/s mode.
80	RX_DV_A/MII_MODE_A	output	Receive data valid indicator for Port A, or when strap pulled high enables RMII or SNI mode.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-80(12x12)
Category	Interface
Pins	80

CAD (KiCad official)

Symbol: DP83849IVSX
Footprint: Package_QFP:TQFP-80_12x12mm_P0.5mm
3D model: TQFP-80(12x12) (KiCad packages3D, STEP)
3D model files: dp83849ivsx-etched.step / dp83849ivsx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83849ivsx.step / dp83849ivsx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (106 pp, sha256 cda2b378740678e3, retrieved 2026-09-24, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF