component
DP83849IVS
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Texas Instruments Ethernet Transceivers, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+116@@ -0,0 +1,116 @@+# DP83849IVS++**Texas Instruments** · Ethernet Transceivers · TQFP-80(12x12)++DP83849IVS from Texas Instruments, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CRS_A/CRS_DV_A/LED_CFG_A | output | Carrier Sense or Carrier Sense/Receive Data Valid asserted high to indicate non-idle receive medium in MII/RMII/SNI modes; also used as LED Configuration strap option. |+| 2 | RX_ER_A/MDIX_EN_A | output | Receive Error output asserted high to indicate invalid symbol detection in 100 Mb/s mode or False Carrier event in RMII mode; also used as MDIX Enable strap option. |+| 3 | COL_A | output | Collision Detect output asserted high to indicate simultaneous transmit and receive activity in half duplex modes or heartbeat in 10BASE-T half duplex mode. |+| 4 | RXD0_A/PHYAD1 | output | Receive Data bit 0 driven synchronously to RX_CLK with valid data when RX_DV or CRS is asserted; also used as PHY Address bit 1 strap during reset. |+| 5 | RXD1_A/PHYAD2 | output | Receive Data bit 1 driven synchronously to RX_CLK with valid data when RX_DV or CRS is asserted; also used as PHY Address bit 2 strap during reset. |+| 6 | COREGND1 | power_in | Core Ground connection for Port A. |+| 7 | PFBIN1 | input | Power Feedback Input connection requiring 0.1 µF capacitor placed close to the pin; fed with power from PFBOUT pin only. |+| 8 | RXD2_A/CLK2MAC_DIS | output | Receive Data bit 2 in MII mode driven synchronously to RX_CLK; also used as CLK2MAC disable strap option. |+| 9 | RXD3_A/ED_EN_A | output | Receive Data bit 3 in MII mode driven synchronously to RX_CLK; also used as Energy Detect enable strap option. |+| 10 | IOGND1 | power_in | I/O Ground connection. |+| 11 | IOVDD1 | power_in | I/O 3.3-V Supply connection. |+| 12 | TX_CLK_A | output | MII Transmit Clock output providing 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode; 10 MHz for 10 Mb/s SNI mode. |+| 13 | TX_EN_A | input | MII/RMII Transmit Enable active high input indicating presence of valid data on TXD[3:0] in MII mode or TXD[1:0] in RMII mode. |+| 14 | TXD0_A | input | Transmit Data bit 0 input accepting data synchronous to TX_CLK in MII/RMII/SNI modes. |+| 15 | TXD1_A | input | Transmit Data bit 1 input accepting data synchronous to TX_CLK in MII/RMII/SNI modes. |+| 16 | TXD2_A | input | Transmit Data bit 2 input accepting data synchronous to TX_CLK in MII/RMII modes. |+| 17 | TXD3_A/SNI_MODE_A | input | Transmit Data bit 3 input in MII mode; also used as SNI Mode strap option for MAC Data Interface configuration. |+| 18 | PWRDOWN_INT_A | input | Power Down active low input for Port A; can be configured as open drain Interrupt output when INT_OE bit is set in MICR register. |+| 19 | LED_LINK_A/AN0_A | bidirectional | Link Status LED output indicating link status in Mode 1 or Link/Activity LED in Mode 2/3; also used as AN0 auto-negotiation strap pin. |+| 20 | LED_SPEED_A/AN1_A | bidirectional | Speed LED output which is ON at 100 Mb/s and OFF at 10 Mb/s; also used as AN1 auto-negotiation strap pin. |+| 21 | LED_ACT/LED_COL/AN_EN_A | bidirectional | Activity LED in Mode 1 or Collision/Duplex LED in Mode 2/3; also used as Auto-Negotiation Enable strap pin. |+| 22 | ANAGND1 | power_in | Analog Ground connection. |+| 23 | TPRDM_A | bidirectional | 10BASE-T or 100BASE-TX differential receive data minus input/output pair with 3.3-V bias requirement for Port A. |+| 24 | TPRDP_A | bidirectional | 10BASE-T or 100BASE-TX differential receive data plus input/output pair with 3.3-V bias requirement for Port A. |+| 25 | CDGND1 | power_in | CD Ground connection for Port A. |+| 26 | TPTDM_A | bidirectional | 10BASE-T or 100BASE-TX differential transmit data minus input/output pair with 3.3-V bias requirement for Port A. |+| 27 | TPTDP_A | bidirectional | 10BASE-T or 100BASE-TX differential transmit data plus input/output pair with 3.3-V bias requirement for Port A. |+| 28 | PFBIN2 | input | Power Feedback Input connection requiring 0.1 µF capacitor placed close to the pin; fed with power from PFBOUT pin only. |+| 29 | ANAGND2 | power_in | Analog Ground connection. |+| 30 | ANA33VDD | power_in | Analog 3.3-V Supply connection. |+| 31 | PFBOUT | power_out | Power Feedback Output providing power to PFBIN1-4 pins; requires 10 µF and 0.1 µF parallel capacitors placed close to the pin. |+| 32 | RBIAS | passive | Bias Resistor Connection requiring 4-87 kΩ 1% resistor to be connected from this pin to GND. |+| 33 | ANAGND3 | power_in | Analog Ground connection. |+| 34 | PFBIN3 | input | Power Feedback Input connection requiring 0.1 µF capacitor placed close to the pin; fed with power from PFBOUT pin only. |+| 35 | TPTDP_B | bidirectional | 10BASE-T or 100BASE-TX differential transmit data plus input/output pair with 3.3-V bias requirement for Port B. |+| 36 | TPTDM_B | bidirectional | 10BASE-T or 100BASE-TX differential transmit data minus input/output pair with 3.3-V bias requirement for Port B. |+| 37 | CDGND2 | power_in | CD Ground connection for Port B. |+| 38 | TPRDP_B | bidirectional | 10BASE-T or 100BASE-TX differential receive data plus input/output pair with 3.3-V bias requirement for Port B. |+| 39 | TPRDM_B | bidirectional | 10BASE-T or 100BASE-TX differential receive data minus input/output pair with 3.3-V bias requirement for Port B. |+| 40 | ANAGND4 | power_in | Analog Ground connection. |+| 41 | LED_ACT/LED_COL/AN_EN_B | bidirectional | Activity LED in Mode 1 or Collision/Duplex LED in Mode 2/3 for Port B; also used as Auto-Negotiation Enable strap pin. |+| 42 | LED_SPEED_B/AN1_B | bidirectional | Speed LED output for Port B which is ON at 100 Mb/s and OFF at 10 Mb/s; also used as AN1 auto-negotiation strap pin. |+| 43 | LED_LINK_B/AN0_B | bidirectional | Link Status LED output for Port B indicating link status in Mode 1 or Link/Activity LED in Mode 2/3; also used as AN0 strap pin. |+| 44 | PWRDOWN_INT_B | input | Power Down active low input for Port B; can be configured as open drain Interrupt output when INT_OE bit is set in MICR register. |+| 45 | TXD3_B/SNI_MODE_B | input | Transmit Data bit 3 input for Port B in MII mode; also used as SNI Mode strap option for MAC Data Interface configuration. |+| 46 | TXD2_B | input | Transmit Data bit 2 input for Port B in MII mode. |+| 47 | TXD1_B | input | Transmit Data bit 1 input for Port B accepting data synchronous to TX_CLK in MII/RMII/SNI modes. |+| 48 | TXD0_B | input | Transmit Data bit 0 input for Port B accepting data synchronous to TX_CLK in MII/RMII/SNI modes. |+| 49 | TX_EN_B | input | Transmit Enable active high input for Port B indicating presence of valid data on TXD[3:0] in MII mode or TXD[1:0] in RMII mode. |+| 50 | TX_CLK_B | output | MII Transmit Clock output for Port B providing 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode; 10 MHz for 10 Mb/s SNI mode. |+| 51 | IOVDD2 | power_in | I/O 3.3-V Supply connection. |+| 52 | IOGND2 | power_in | I/O Ground connection. |+| 53 | RXD3_B/ED_EN_B | output | Receive Data bit 3 output for Port B in MII mode; also used as Energy Detect enable strap option. |+| 54 | PFBIN4 | input | Power Feedback Input connection requiring 0.1 µF capacitor placed close to the pin; fed with power from PFBOUT pin only. |+| 55 | COREGND2 | power_in | Core Ground connection for Port B. |+| 56 | RXD2_B/EXTENDER_EN | output | Receive Data bit 2 output for Port B in MII mode; also used as Extender Mode enable strap option. |+| 57 | RXD1_B/PHYAD4 | output | Receive Data bit 1 output for Port B driven synchronously to RX_CLK; also used as PHY Address bit 4 strap during reset. |+| 58 | RXD0_B/PHYAD3 | output | Receive Data bit 0 output for Port B driven synchronously to RX_CLK; also used as PHY Address bit 3 strap during reset. |+| 59 | COL_B | output | Collision Detect output for Port B asserted high to indicate simultaneous transmit and receive activity in half duplex modes. |+| 60 | RX_ER_B/MDIX_EN_B | output | Receive Error output for Port B asserted high to indicate invalid symbol detection or False Carrier event; also used as MDIX Enable strap option. |+| 61 | CRS_B/CRS_DV_B/LED_CFG_B | output | Carrier Sense or Carrier Sense/Receive Data Valid for Port B asserted high to indicate non-idle receive medium in MII/SNI modes; also used as LED Configuration strap option. |+| 62 | RX_DV_B/MII_MODE_B | output | Receive Data Valid output for Port B asserted high when valid data is present on RXD[1:0] in RMII mode; also used as MII Mode strap option. |+| 63 | RX_CLK_B | output | Receive Clock output for Port B providing 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode in MII/SNI operation. |+| 64 | IOGND3 | power_in | I/O Ground connection. |+| 65 | IOVDD3 | power_in | I/O 3.3-V Supply connection. |+| 66 | MDIO | bidirectional | Management Data I/O bi-directional serial interface signal sourced by station management entity or PHY; requires 1.5-kΩ pullup resistor. |+| 67 | MDC | input | Management Data Clock synchronous clock to MDIO interface with maximum clock rate of 25 MHz and no minimum clock rate. |+| 68 | CLK2MAC | output | Clock to MAC output providing 25 MHz in MII mode or 50 MHz in RMII mode; can be disabled via CLK2MAC_DIS strap option. |+| 69 | X2 | output | Crystal Oscillator Output connection for external 25 MHz crystal resonator device; must be left unconnected if external CMOS oscillator is used. |+| 70 | X1 | input | Crystal/Oscillator Input primary clock reference for 25 MHz 0.005% (+50 ppm) clock source or 50 MHz CMOS-level oscillator in RMII mode. |+| 71 | RESET_N | input | Reset active low input; asserting low for at least 1 µs forces reset process to occur and re-initializes all registers and strap options. |+| 72 | TCK | input | Test Clock input for JTAG interface with weak internal pullup. |+| 73 | TDO | output | Test Data Output for JTAG interface. |+| 74 | TMS | input | Test Mode Select input for JTAG interface with weak internal pullup. |+| 75 | TRSTN | input | Test Reset active low input for JTAG interface with weak internal pullup. |+| 76 | TDI | input | Test Data Input for JTAG interface with weak internal pullup. |+| 77 | IOGND4 | power_in | I/O Ground connection. |+| 78 | IOVDD4 | power_in | I/O 3.3-V Supply connection. |+| 79 | RX_CLK_A | output | MII Receive Clock output for Port A providing 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode in MII/SNI operation. |+| 80 | RX_DV_A/MII_MODE_A | output | Receive Data Valid output for Port A asserted high when valid data is present on RXD[1:0] in RMII mode; also used as MII Mode strap option. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-80(12x12) |+| Category | Interface |+| Pins | 80 |++## CAD (KiCad official)++- Symbol: `DP83849IVS`+- Footprint: `Package_QFP:TQFP-80_12x12mm_P0.5mm`+- 3D model: TQFP-80(12x12) (KiCad packages3D, STEP)+- 3D model files: `dp83849ivs-etched.step` / `dp83849ivs-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83849ivs.step` / `dp83849ivs.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83849i) (106 pp, sha256 `cda2b378740678e3`, retrieved 2026-10-01, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dp83849ivs-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "dp83849ivs",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dp83849ivs.kicad_sym",+ "dp83849ivs.kicad_mod",+ "dp83849ivs.glb",+ "dp83849ivs.step",+ "dp83849ivs.lbr",+ "docs/hero.png",+ "docs/dp83849ivs-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DP83849IVS",+ "manufacturer": "Texas Instruments",+ "package": "TQFP-80(12x12)",+ "pin_count": 80,+ "category": "Interface",+ "subcategory": "Ethernet Transceivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dp83849i",+ "parts": {+ "symbol": "dp83849ivs.kicad_sym",+ "footprint": "dp83849ivs.kicad_mod",+ "model_3d": "dp83849ivs-etched.glb",+ "model_3d_plain": "dp83849ivs.glb",+ "model_3d_step": "dp83849ivs-etched.step",+ "model_3d_step_plain": "dp83849ivs.step",+ "lbr": "dp83849ivs.lbr"+ },+ "distributor_links": {+ "lcsc": "C1543897"+ },+ "distributor_check": {+ "checked_at": "2026-10-01T06:32:07Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CRS_A/CRS_DV_A/LED_CFG_A",+ "type": "output",+ "description": "Carrier Sense or Carrier Sense/Receive Data Valid asserted high to indicate non-idle receive medium in MII/RMII/SNI modes; also used as LED Configuration strap option."+ },+ {+ "number": "2",+ "name": "RX_ER_A/MDIX_EN_A",+ "type": "output",+ "description": "Receive Error output asserted high to indicate invalid symbol detection in 100 Mb/s mode or False Carrier event in RMII mode; also used as MDIX Enable strap option."+ },+ {+ "number": "3",+ "name": "COL_A",+ "type": "output",+ "description": "Collision Detect output asserted high to indicate simultaneous transmit and receive activity in half duplex modes or heartbeat in 10BASE-T half duplex mode."+ },+ {+ "number": "4",+ "name": "RXD0_A/PHYAD1",+ "type": "output",+ "description": "Receive Data bit 0 driven synchronously to RX_CLK with valid data when RX_DV or CRS is asserted; also used as PHY Address bit 1 strap during reset."+ },+ {+ "number": "5",+ "name": "RXD1_A/PHYAD2",+ "type": "output",+ "description": "Receive Data bit 1 driven synchronously to RX_CLK with valid data when RX_DV or CRS is asserted; also used as PHY Address bit 2 strap during reset."+ },+ {+ "number": "6",+ "name": "COREGND1",+ "type": "power_in",+ "description": "Core Ground connection for Port A."+ },+ {+ "number": "7",+ "name": "PFBIN1",+ "type": "input",+ "description": "Power Feedback Input connection requiring 0.1 µF capacitor placed close to the pin; fed with power from PFBOUT pin only."+ },+ {+ "number": "8",+ "name": "RXD2_A/CLK2MAC_DIS",+ "type": "output",+ "description": "Receive Data bit 2 in MII mode driven synchronously to RX_CLK; also used as CLK2MAC disable strap option."+ },+ {+ "number": "9",+ "name": "RXD3_A/ED_EN_A",+ "type": "output",+ "description": "Receive Data bit 3 in MII mode driven synchronously to RX_CLK; also used as Energy Detect enable strap option."+ },+ {+ "number": "10",+ "name": "IOGND1",+ "type": "power_in",+ "description": "I/O Ground connection."+ },+ {+ "number": "11",+ "name": "IOVDD1",+ "type": "power_in",+ "description": "I/O 3.3-V Supply connection."+ },+ {+ "number": "12",+ "name": "TX_CLK_A",+ "type": "output",+ "description": "MII Transmit Clock output providing 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode; 10 MHz for 10 Mb/s SNI mode."+ },+ {+ "number": "13",+ "name": "TX_EN_A",+ "type": "input",+ "description": "MII/RMII Transmit Enable active high input indicating presence of valid data on TXD[3:0] in MII mode or TXD[1:0] in RMII mode."+ },+ {+ "number": "14",+ "name": "TXD0_A",+ "type": "input",+ "description": "Transmit Data bit 0 input accepting data synchronous to TX_CLK in MII/RMII/SNI modes."+ },+ {+ "number": "15",+ "name": "TXD1_A",+ "type": "input",+ "description": "Transmit Data bit 1 input accepting data synchronous to TX_CLK in MII/RMII/SNI modes."+ },+ {+ "number": "16",+ "name": "TXD2_A",+ "type": "input",+ "description": "Transmit Data bit 2 input accepting data synchronous to TX_CLK in MII/RMII modes."+ },+ {+ "number": "17",+ "name": "TXD3_A/SNI_MODE_A",+ "type": "input",+ "description": "Transmit Data bit 3 input in MII mode; also used as SNI Mode strap option for MAC Data Interface configuration."+ },+ {+ "number": "18",+ "name": "PWRDOWN_INT_A",+ "type": "input",+ "description": "Power Down active low input for Port A; can be configured as open drain Interrupt output when INT_OE bit is set in MICR register."+ },+ {+ "number": "19",+ "name": "LED_LINK_A/AN0_A",+ "type": "bidirectional",+ "description": "Link Status LED output indicating link status in Mode 1 or Link/Activity LED in Mode 2/3; also used as AN0 auto-negotiation strap pin."+ },+ {+ "number": "20",+ "name": "LED_SPEED_A/AN1_A",+ "type": "bidirectional",+ "description": "Speed LED output which is ON at 100 Mb/s and OFF at 10 Mb/s; also used as AN1 auto-negotiation strap pin."+ },+ {+ "number": "21",+ "name": "LED_ACT/LED_COL/AN_EN_A",+ "type": "bidirectional",+ "description": "Activity LED in Mode 1 or Collision/Duplex LED in Mode 2/3; also used as Auto-Negotiation Enable strap pin."+ },+ {+ "number": "22",+ "name": "ANAGND1",+ "type": "power_in",+ "description": "Analog Ground connection."+ },+ {+ "number": "23",+ "name": "TPRDM_A",+ "type": "bidirectional",+ "description": "10BASE-T or 100BASE-TX differential receive data minus input/output pair with 3.3-V bias requirement for Port A."+ },+ {+ "number": "24",+ "name": "TPRDP_A",+ "type": "bidirectional",+ "description": "10BASE-T or 100BASE-TX differential receive data plus input/output pair with 3.3-V bias requirement for Port A."+ },+ {+ "number": "25",+ "name": "CDGND1",+ "type": "power_in",+ "description": "CD Ground connection for Port A."+ },+ {+ "number": "26",+ "name": "TPTDM_A",+ "type": "bidirectional",+ "description": "10BASE-T or 100BASE-TX differential transmit data minus input/output pair with 3.3-V bias requirement for Port A."+ },+ {+ "number": "27",+ "name": "TPTDP_A",+ "type": "bidirectional",+ "description": "10BASE-T or 100BASE-TX differential transmit data plus input/output pair with 3.3-V bias requirement for Port A."+ },+ {+ "number": "28",+ "name": "PFBIN2",+ "type": "input",+ "description": "Power Feedback Input connection requiring 0.1 µF capacitor placed close to the pin; fed with power from PFBOUT pin only."+ },+ {+ "number": "29",+ "name": "ANAGND2",+ "type": "power_in",+ "description": "Analog Ground connection."+ },+ {+ "number": "30",+ "name": "ANA33VDD",+ "type": "power_in",+ "description": "Analog 3.3-V Supply connection."+ },+ {+ "number": "31",+ "name": "PFBOUT",+ "type": "power_out",+ "description": "Power Feedback Output providing power to PFBIN1-4 pins; requires 10 µF and 0.1 µF parallel capacitors placed close to the pin."+ },+ {+ "number": "32",+ "name": "RBIAS",+ "type": "passive",+ "description": "Bias Resistor Connection requiring 4-87 kΩ 1% resistor to be connected from this pin to GND."+ },+ {+ "number": "33",+ "name": "ANAGND3",+ "type": "power_in",+ "description": "Analog Ground connection."+ },+ {+ "number": "34",+ "name": "PFBIN3",+ "type": "input",+ "description": "Power Feedback Input connection requiring 0.1 µF capacitor placed close to the pin; fed with power from PFBOUT pin only."+ },+ {+ "number": "35",+ "name": "TPTDP_B",+ "type": "bidirectional",+ "description": "10BASE-T or 100BASE-TX differential transmit data plus input/output pair with 3.3-V bias requirement for Port B."+ },+ {+ "number": "36",+ "name": "TPTDM_B",+ "type": "bidirectional",+ "description": "10BASE-T or 100BASE-TX differential transmit data minus input/output pair with 3.3-V bias requirement for Port B."+ },+ {+ "number": "37",+ "name": "CDGND2",+ "type": "power_in",+ "description": "CD Ground connection for Port B."+ },+ {+ "number": "38",+ "name": "TPRDP_B",+ "type": "bidirectional",+ "description": "10BASE-T or 100BASE-TX differential receive data plus input/output pair with 3.3-V bias requirement for Port B."+ },+ {+ "number": "39",+ "name": "TPRDM_B",+ "type": "bidirectional",+ "description": "10BASE-T or 100BASE-TX differential receive data minus input/output pair with 3.3-V bias requirement for Port B."+ },+ {+ "number": "40",+ "name": "ANAGND4",+ "type": "power_in",+ "description": "Analog Ground connection."+ },+ {+ "number": "41",+ "name": "LED_ACT/LED_COL/AN_EN_B",+ "type": "bidirectional",+ "description": "Activity LED in Mode 1 or Collision/Duplex LED in Mode 2/3 for Port B; also used as Auto-Negotiation Enable strap pin."+ },+ {+ "number": "42",+ "name": "LED_SPEED_B/AN1_B",+ "type": "bidirectional",+ "description": "Speed LED output for Port B which is ON at 100 Mb/s and OFF at 10 Mb/s; also used as AN1 auto-negotiation strap pin."+ },+ {+ "number": "43",+ "name": "LED_LINK_B/AN0_B",+ "type": "bidirectional",+ "description": "Link Status LED output for Port B indicating link status in Mode 1 or Link/Activity LED in Mode 2/3; also used as AN0 strap pin."+ },+ {+ "number": "44",+ "name": "PWRDOWN_INT_B",+ "type": "input",+ "description": "Power Down active low input for Port B; can be configured as open drain Interrupt output when INT_OE bit is set in MICR register."+ },+ {+ "number": "45",+ "name": "TXD3_B/SNI_MODE_B",+ "type": "input",+ "description": "Transmit Data bit 3 input for Port B in MII mode; also used as SNI Mode strap option for MAC Data Interface configuration."+ },+ {+ "number": "46",+ "name": "TXD2_B",+ "type": "input",+ "description": "Transmit Data bit 2 input for Port B in MII mode."+ },+ {+ "number": "47",+ "name": "TXD1_B",+ "type": "input",+ "description": "Transmit Data bit 1 input for Port B accepting data synchronous to TX_CLK in MII/RMII/SNI modes."+ },+ {+ "number": "48",+ "name": "TXD0_B",+ "type": "input",+ "description": "Transmit Data bit 0 input for Port B accepting data synchronous to TX_CLK in MII/RMII/SNI modes."+ },+ {+ "number": "49",+ "name": "TX_EN_B",+ "type": "input",+ "description": "Transmit Enable active high input for Port B indicating presence of valid data on TXD[3:0] in MII mode or TXD[1:0] in RMII mode."+ },+ {+ "number": "50",+ "name": "TX_CLK_B",+ "type": "output",+ "description": "MII Transmit Clock output for Port B providing 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode; 10 MHz for 10 Mb/s SNI mode."+ },+ {+ "number": "51",+ "name": "IOVDD2",+ "type": "power_in",+ "description": "I/O 3.3-V Supply connection."+ },+ {+ "number": "52",+ "name": "IOGND2",+ "type": "power_in",+ "description": "I/O Ground connection."+ },+ {+ "number": "53",+ "name": "RXD3_B/ED_EN_B",+ "type": "output",+ "description": "Receive Data bit 3 output for Port B in MII mode; also used as Energy Detect enable strap option."+ },+ {+ "number": "54",+ "name": "PFBIN4",+ "type": "input",+ "description": "Power Feedback Input connection requiring 0.1 µF capacitor placed close to the pin; fed with power from PFBOUT pin only."+ },+ {+ "number": "55",+ "name": "COREGND2",+ "type": "power_in",+ "description": "Core Ground connection for Port B."+ },+ {+ "number": "56",+ "name": "RXD2_B/EXTENDER_EN",+ "type": "output",+ "description": "Receive Data bit 2 output for Port B in MII mode; also used as Extender Mode enable strap option."+ },+ {+ "number": "57",+ "name": "RXD1_B/PHYAD4",+ "type": "output",+ "description": "Receive Data bit 1 output for Port B driven synchronously to RX_CLK; also used as PHY Address bit 4 strap during reset."+ },+ {+ "number": "58",+ "name": "RXD0_B/PHYAD3",+ "type": "output",+ "description": "Receive Data bit 0 output for Port B driven synchronously to RX_CLK; also used as PHY Address bit 3 strap during reset."+ },+ {+ "number": "59",+ "name": "COL_B",+ "type": "output",+ "description": "Collision Detect output for Port B asserted high to indicate simultaneous transmit and receive activity in half duplex modes."+ },+ {+ "number": "60",+ "name": "RX_ER_B/MDIX_EN_B",+ "type": "output",+ "description": "Receive Error output for Port B asserted high to indicate invalid symbol detection or False Carrier event; also used as MDIX Enable strap option."+ },+ {+ "number": "61",+ "name": "CRS_B/CRS_DV_B/LED_CFG_B",+ "type": "output",+ "description": "Carrier Sense or Carrier Sense/Receive Data Valid for Port B asserted high to indicate non-idle receive medium in MII/SNI modes; also used as LED Configuration strap option."+ },+ {+ "number": "62",+ "name": "RX_DV_B/MII_MODE_B",+ "type": "output",+ "description": "Receive Data Valid output for Port B asserted high when valid data is present on RXD[1:0] in RMII mode; also used as MII Mode strap option."+ },+ {+ "number": "63",+ "name": "RX_CLK_B",+ "type": "output",+ "description": "Receive Clock output for Port B providing 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode in MII/SNI operation."+ },+ {+ "number": "64",+ "name": "IOGND3",+ "type": "power_in",+ "description": "I/O Ground connection."+ },+ {+ "number": "65",+ "name": "IOVDD3",+ "type": "power_in",+ "description": "I/O 3.3-V Supply connection."+ },+ {+ "number": "66",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Management Data I/O bi-directional serial interface signal sourced by station management entity or PHY; requires 1.5-kΩ pullup resistor."+ },+ {+ "number": "67",+ "name": "MDC",+ "type": "input",+ "description": "Management Data Clock synchronous clock to MDIO interface with maximum clock rate of 25 MHz and no minimum clock rate."+ },+ {+ "number": "68",+ "name": "CLK2MAC",+ "type": "output",+ "description": "Clock to MAC output providing 25 MHz in MII mode or 50 MHz in RMII mode; can be disabled via CLK2MAC_DIS strap option."+ },+ {+ "number": "69",+ "name": "X2",+ "type": "output",+ "description": "Crystal Oscillator Output connection for external 25 MHz crystal resonator device; must be left unconnected if external CMOS oscillator is used."+ },+ {+ "number": "70",+ "name": "X1",+ "type": "input",+ "description": "Crystal/Oscillator Input primary clock reference for 25 MHz 0.005% (+50 ppm) clock source or 50 MHz CMOS-level oscillator in RMII mode."+ },+ {+ "number": "71",+ "name": "RESET_N",+ "type": "input",+ "description": "Reset active low input; asserting low for at least 1 µs forces reset process to occur and re-initializes all registers and strap options."+ },+ {+ "number": "72",+ "name": "TCK",+ "type": "input",+ "description": "Test Clock input for JTAG interface with weak internal pullup."+ },+ {+ "number": "73",+ "name": "TDO",+ "type": "output",+ "description": "Test Data Output for JTAG interface."+ },+ {+ "number": "74",+ "name": "TMS",+ "type": "input",+ "description": "Test Mode Select input for JTAG interface with weak internal pullup."+ },+ {+ "number": "75",+ "name": "TRSTN",+ "type": "input",+ "description": "Test Reset active low input for JTAG interface with weak internal pullup."+ },+ {+ "number": "76",+ "name": "TDI",+ "type": "input",+ "description": "Test Data Input for JTAG interface with weak internal pullup."+ },+ {+ "number": "77",+ "name": "IOGND4",+ "type": "power_in",+ "description": "I/O Ground connection."+ },+ {+ "number": "78",+ "name": "IOVDD4",+ "type": "power_in",+ "description": "I/O 3.3-V Supply connection."+ },+ {+ "number": "79",+ "name": "RX_CLK_A",+ "type": "output",+ "description": "MII Receive Clock output for Port A providing 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode in MII/SNI operation."+ },+ {+ "number": "80",+ "name": "RX_DV_A/MII_MODE_A",+ "type": "output",+ "description": "Receive Data Valid output for Port A asserted high when valid data is present on RXD[1:0] in RMII mode; also used as MII Mode strap option."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 22,+ "cost_usd": 0.2597,+ "at": "2026-10-01T06:31:38"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dp83849i",+ "pages": 106,+ "sha256": "cda2b378740678e3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 80,+ "described": 80,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}