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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83849IVS

Texas Instruments · Ethernet Transceivers · TQFP-80(12x12)

DP83849IVS from Texas Instruments, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CRS_A/CRS_DV_A/LED_CFG_A	output	Carrier Sense or Carrier Sense/Receive Data Valid asserted high to indicate non-idle receive medium in MII/RMII/SNI modes; also used as LED Configuration strap option.
2	RX_ER_A/MDIX_EN_A	output	Receive Error output asserted high to indicate invalid symbol detection in 100 Mb/s mode or False Carrier event in RMII mode; also used as MDIX Enable strap option.
3	COL_A	output	Collision Detect output asserted high to indicate simultaneous transmit and receive activity in half duplex modes or heartbeat in 10BASE-T half duplex mode.
4	RXD0_A/PHYAD1	output	Receive Data bit 0 driven synchronously to RX_CLK with valid data when RX_DV or CRS is asserted; also used as PHY Address bit 1 strap during reset.
5	RXD1_A/PHYAD2	output	Receive Data bit 1 driven synchronously to RX_CLK with valid data when RX_DV or CRS is asserted; also used as PHY Address bit 2 strap during reset.
6	COREGND1	power_in	Core Ground connection for Port A.
7	PFBIN1	input	Power Feedback Input connection requiring 0.1 µF capacitor placed close to the pin; fed with power from PFBOUT pin only.
8	RXD2_A/CLK2MAC_DIS	output	Receive Data bit 2 in MII mode driven synchronously to RX_CLK; also used as CLK2MAC disable strap option.
9	RXD3_A/ED_EN_A	output	Receive Data bit 3 in MII mode driven synchronously to RX_CLK; also used as Energy Detect enable strap option.
10	IOGND1	power_in	I/O Ground connection.
11	IOVDD1	power_in	I/O 3.3-V Supply connection.
12	TX_CLK_A	output	MII Transmit Clock output providing 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode; 10 MHz for 10 Mb/s SNI mode.
13	TX_EN_A	input	MII/RMII Transmit Enable active high input indicating presence of valid data on TXD[3:0] in MII mode or TXD[1:0] in RMII mode.
14	TXD0_A	input	Transmit Data bit 0 input accepting data synchronous to TX_CLK in MII/RMII/SNI modes.
15	TXD1_A	input	Transmit Data bit 1 input accepting data synchronous to TX_CLK in MII/RMII/SNI modes.
16	TXD2_A	input	Transmit Data bit 2 input accepting data synchronous to TX_CLK in MII/RMII modes.
17	TXD3_A/SNI_MODE_A	input	Transmit Data bit 3 input in MII mode; also used as SNI Mode strap option for MAC Data Interface configuration.
18	PWRDOWN_INT_A	input	Power Down active low input for Port A; can be configured as open drain Interrupt output when INT_OE bit is set in MICR register.
19	LED_LINK_A/AN0_A	bidirectional	Link Status LED output indicating link status in Mode 1 or Link/Activity LED in Mode 2/3; also used as AN0 auto-negotiation strap pin.
20	LED_SPEED_A/AN1_A	bidirectional	Speed LED output which is ON at 100 Mb/s and OFF at 10 Mb/s; also used as AN1 auto-negotiation strap pin.
21	LED_ACT/LED_COL/AN_EN_A	bidirectional	Activity LED in Mode 1 or Collision/Duplex LED in Mode 2/3; also used as Auto-Negotiation Enable strap pin.
22	ANAGND1	power_in	Analog Ground connection.
23	TPRDM_A	bidirectional	10BASE-T or 100BASE-TX differential receive data minus input/output pair with 3.3-V bias requirement for Port A.
24	TPRDP_A	bidirectional	10BASE-T or 100BASE-TX differential receive data plus input/output pair with 3.3-V bias requirement for Port A.
25	CDGND1	power_in	CD Ground connection for Port A.
26	TPTDM_A	bidirectional	10BASE-T or 100BASE-TX differential transmit data minus input/output pair with 3.3-V bias requirement for Port A.
27	TPTDP_A	bidirectional	10BASE-T or 100BASE-TX differential transmit data plus input/output pair with 3.3-V bias requirement for Port A.
28	PFBIN2	input	Power Feedback Input connection requiring 0.1 µF capacitor placed close to the pin; fed with power from PFBOUT pin only.
29	ANAGND2	power_in	Analog Ground connection.
30	ANA33VDD	power_in	Analog 3.3-V Supply connection.
31	PFBOUT	power_out	Power Feedback Output providing power to PFBIN1-4 pins; requires 10 µF and 0.1 µF parallel capacitors placed close to the pin.
32	RBIAS	passive	Bias Resistor Connection requiring 4-87 kΩ 1% resistor to be connected from this pin to GND.
33	ANAGND3	power_in	Analog Ground connection.
34	PFBIN3	input	Power Feedback Input connection requiring 0.1 µF capacitor placed close to the pin; fed with power from PFBOUT pin only.
35	TPTDP_B	bidirectional	10BASE-T or 100BASE-TX differential transmit data plus input/output pair with 3.3-V bias requirement for Port B.
36	TPTDM_B	bidirectional	10BASE-T or 100BASE-TX differential transmit data minus input/output pair with 3.3-V bias requirement for Port B.
37	CDGND2	power_in	CD Ground connection for Port B.
38	TPRDP_B	bidirectional	10BASE-T or 100BASE-TX differential receive data plus input/output pair with 3.3-V bias requirement for Port B.
39	TPRDM_B	bidirectional	10BASE-T or 100BASE-TX differential receive data minus input/output pair with 3.3-V bias requirement for Port B.
40	ANAGND4	power_in	Analog Ground connection.
41	LED_ACT/LED_COL/AN_EN_B	bidirectional	Activity LED in Mode 1 or Collision/Duplex LED in Mode 2/3 for Port B; also used as Auto-Negotiation Enable strap pin.
42	LED_SPEED_B/AN1_B	bidirectional	Speed LED output for Port B which is ON at 100 Mb/s and OFF at 10 Mb/s; also used as AN1 auto-negotiation strap pin.
43	LED_LINK_B/AN0_B	bidirectional	Link Status LED output for Port B indicating link status in Mode 1 or Link/Activity LED in Mode 2/3; also used as AN0 strap pin.
44	PWRDOWN_INT_B	input	Power Down active low input for Port B; can be configured as open drain Interrupt output when INT_OE bit is set in MICR register.
45	TXD3_B/SNI_MODE_B	input	Transmit Data bit 3 input for Port B in MII mode; also used as SNI Mode strap option for MAC Data Interface configuration.
46	TXD2_B	input	Transmit Data bit 2 input for Port B in MII mode.
47	TXD1_B	input	Transmit Data bit 1 input for Port B accepting data synchronous to TX_CLK in MII/RMII/SNI modes.
48	TXD0_B	input	Transmit Data bit 0 input for Port B accepting data synchronous to TX_CLK in MII/RMII/SNI modes.
49	TX_EN_B	input	Transmit Enable active high input for Port B indicating presence of valid data on TXD[3:0] in MII mode or TXD[1:0] in RMII mode.
50	TX_CLK_B	output	MII Transmit Clock output for Port B providing 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode; 10 MHz for 10 Mb/s SNI mode.
51	IOVDD2	power_in	I/O 3.3-V Supply connection.
52	IOGND2	power_in	I/O Ground connection.
53	RXD3_B/ED_EN_B	output	Receive Data bit 3 output for Port B in MII mode; also used as Energy Detect enable strap option.
54	PFBIN4	input	Power Feedback Input connection requiring 0.1 µF capacitor placed close to the pin; fed with power from PFBOUT pin only.
55	COREGND2	power_in	Core Ground connection for Port B.
56	RXD2_B/EXTENDER_EN	output	Receive Data bit 2 output for Port B in MII mode; also used as Extender Mode enable strap option.
57	RXD1_B/PHYAD4	output	Receive Data bit 1 output for Port B driven synchronously to RX_CLK; also used as PHY Address bit 4 strap during reset.
58	RXD0_B/PHYAD3	output	Receive Data bit 0 output for Port B driven synchronously to RX_CLK; also used as PHY Address bit 3 strap during reset.
59	COL_B	output	Collision Detect output for Port B asserted high to indicate simultaneous transmit and receive activity in half duplex modes.
60	RX_ER_B/MDIX_EN_B	output	Receive Error output for Port B asserted high to indicate invalid symbol detection or False Carrier event; also used as MDIX Enable strap option.
61	CRS_B/CRS_DV_B/LED_CFG_B	output	Carrier Sense or Carrier Sense/Receive Data Valid for Port B asserted high to indicate non-idle receive medium in MII/SNI modes; also used as LED Configuration strap option.
62	RX_DV_B/MII_MODE_B	output	Receive Data Valid output for Port B asserted high when valid data is present on RXD[1:0] in RMII mode; also used as MII Mode strap option.
63	RX_CLK_B	output	Receive Clock output for Port B providing 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode in MII/SNI operation.
64	IOGND3	power_in	I/O Ground connection.
65	IOVDD3	power_in	I/O 3.3-V Supply connection.
66	MDIO	bidirectional	Management Data I/O bi-directional serial interface signal sourced by station management entity or PHY; requires 1.5-kΩ pullup resistor.
67	MDC	input	Management Data Clock synchronous clock to MDIO interface with maximum clock rate of 25 MHz and no minimum clock rate.
68	CLK2MAC	output	Clock to MAC output providing 25 MHz in MII mode or 50 MHz in RMII mode; can be disabled via CLK2MAC_DIS strap option.
69	X2	output	Crystal Oscillator Output connection for external 25 MHz crystal resonator device; must be left unconnected if external CMOS oscillator is used.
70	X1	input	Crystal/Oscillator Input primary clock reference for 25 MHz 0.005% (+50 ppm) clock source or 50 MHz CMOS-level oscillator in RMII mode.
71	RESET_N	input	Reset active low input; asserting low for at least 1 µs forces reset process to occur and re-initializes all registers and strap options.
72	TCK	input	Test Clock input for JTAG interface with weak internal pullup.
73	TDO	output	Test Data Output for JTAG interface.
74	TMS	input	Test Mode Select input for JTAG interface with weak internal pullup.
75	TRSTN	input	Test Reset active low input for JTAG interface with weak internal pullup.
76	TDI	input	Test Data Input for JTAG interface with weak internal pullup.
77	IOGND4	power_in	I/O Ground connection.
78	IOVDD4	power_in	I/O 3.3-V Supply connection.
79	RX_CLK_A	output	MII Receive Clock output for Port A providing 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode in MII/SNI operation.
80	RX_DV_A/MII_MODE_A	output	Receive Data Valid output for Port A asserted high when valid data is present on RXD[1:0] in RMII mode; also used as MII Mode strap option.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-80(12x12)
Category	Interface
Pins	80

CAD (KiCad official)

Symbol: DP83849IVS
Footprint: Package_QFP:TQFP-80_12x12mm_P0.5mm
3D model: TQFP-80(12x12) (KiCad packages3D, STEP)
3D model files: dp83849ivs-etched.step / dp83849ivs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83849ivs.step / dp83849ivs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (106 pp, sha256 cda2b378740678e3, retrieved 2026-10-01, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF