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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83849IFVS

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TQFP-80(12x12)

DP83849IFVS from Texas Instruments, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CRS_A/CRS_DV_A/LED_CFG_A	output	MII Carrier Sense or RMII Carrier Sense/Data Valid signal; asserted high when receive medium is non-idle.
2	RX_ER_A/MDIX_EN_A	output	MII/RMII Receive Error indicator; asserted high to indicate invalid symbols in received packets or false carrier events.
3	COL_A/FX_EN_A	output	Collision Detect signal in half-duplex modes; asserted high for simultaneous transmit/receive activity or heartbeat in 10BASE-T.
4	RXD0_A/PHYAD1	output	MII Receive Data bit 0; driven synchronously to RX_CLK at 25 MHz (100 Mb/s) or 2.5 MHz (10 Mb/s) when RX_DV asserted.
5	RXD1_A/PHYAD2	output	MII Receive Data bit 1; driven synchronously to RX_CLK at 25 MHz (100 Mb/s) or 2.5 MHz (10 Mb/s) when RX_DV asserted.
6	COREGND1	power_in	Core circuit ground connection for internal logic circuits.
7	PFBIN1	power_in	Power Feedback Input pin; fed with power from PFBOUT with 0.1µF bypass capacitor required.
8	RXD2_A/CLK2MAC_DIS	output	MII Receive Data bit 2; driven synchronously to RX_CLK at 25 MHz (100 Mb/s) or 2.5 MHz (10 Mb/s) when RX_DV asserted.
9	RXD3_A/ED_EN_A	output	MII Receive Data bit 3; driven synchronously to RX_CLK at 25 MHz (100 Mb/s) or 2.5 MHz (10 Mb/s) when RX_DV asserted.
10	IOGND1	power_in	I/O circuit ground connection; provides ground reference for 3.3V I/O logic.
11	IOVDD1	power_in	I/O circuit 3.3V power supply; one of four I/O power supply pins for 3.3V logic.
12	TX_CLK_A	output	MII Transmit Clock output; 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, unused in RMII mode.
13	TX_EN_A	input	MII Transmit Enable input; active high indicates valid transmit data present on TXD[3:0].
14	TXD0_A	input	MII Transmit Data bit 0; input sampled synchronously to TX_CLK (2.5 MHz to 25 MHz depending on mode).
15	TXD1_A	input	MII Transmit Data bit 1; input sampled synchronously to TX_CLK (2.5 MHz to 25 MHz depending on mode).
16	TXD2_A	input	MII Transmit Data bit 2; input sampled synchronously to TX_CLK (2.5 MHz to 25 MHz depending on mode).
17	TXD3_A/SNI_MODE_A	input	MII Transmit Data bit 3; input sampled synchronously to TX_CLK (2.5 MHz to 25 MHz depending on mode).
18	PWRDOWN_INT_A	input	Port A Power Down/Interrupt control; active low input for power down mode or open-drain output for interrupt signaling.
19	LED_LINK_A/AN0_A	output	Port A Link status LED output; indicates link presence (mode 1) or transmit/receive activity with link (modes 2-3).
20	LED_SPEED_A/FXSD_A/AN1_A	output	Port A Speed indicator LED output; asserted high for 100 Mb/s operation and low for 10 Mb/s operation.
21	LED_ACT/LED_COL/AN_EN_A	output	Port A Activity or Collision LED output; indicates activity in mode 1 or collision/duplex status in modes 2-3.
22	ANAGND1	power_in	Analog circuit ground connection; one of four analog ground pins.
23	TPRDM_A/FXRDM_A	bidirectional	10BASE-T/100BASE-TX/100BASE-FX Receive Data pair minus; differential input for PMD receive or auto-MDIX transmit.
24	TPRDP_A/FXRDP_A	bidirectional	10BASE-T/100BASE-TX/100BASE-FX Receive Data pair plus; differential input for PMD receive or auto-MDIX transmit.
25	CDGND1	power_in	Collision Detect circuit ground connection.
26	TPTDM_A/FXTDM_A	bidirectional	10BASE-T/100BASE-TX/100BASE-FX Transmit Data pair minus; differential output for PMD transmit or auto-MDIX receive.
27	TPTDP_A/FXTDP_A	bidirectional	10BASE-T/100BASE-TX/100BASE-FX Transmit Data pair plus; differential output for PMD transmit or auto-MDIX receive.
28	PFBIN2	power_in	Power Feedback Input pin; fed with power from PFBOUT with 0.1µF bypass capacitor required.
29	ANAGND2	power_in	Analog circuit ground connection; one of four analog ground pins.
30	ANA33VDD	power_in	Analog 3.3V power supply; provides power to analog circuit blocks.
31	PFBOUT	power_out	Power Feedback Output; connect to PFBIN1/2/3/4 with 10µF and 0.1µF parallel bypass capacitors.
32	RBIAS	input	Bias Resistor Connection; connect 4.87 kΩ ±1% resistor from this pin to ground for transceiver biasing.
33	ANAGND3	power_in	Analog circuit ground connection; one of four analog ground pins.
34	PFBIN3	power_in	Power Feedback Input pin; fed with power from PFBOUT with 0.1µF bypass capacitor required.
35	TPTDP_B/FXTDP_B	bidirectional	Port B 10BASE-T/100BASE-TX/100BASE-FX Transmit Data pair plus; differential output for PMD transmit or auto-MDIX receive.
36	TPTDM_B/FXTDM_B	bidirectional	Port B 10BASE-T/100BASE-TX/100BASE-FX Transmit Data pair minus; differential output for PMD transmit or auto-MDIX receive.
37	CDGND2	power_in	Collision Detect circuit ground connection.
38	TPRDP_B/FXRDP_B	bidirectional	Port B 10BASE-T/100BASE-TX/100BASE-FX Receive Data pair plus; differential input for PMD receive or auto-MDIX transmit.
39	TPRDM_B/FXRDM_B	bidirectional	Port B 10BASE-T/100BASE-TX/100BASE-FX Receive Data pair minus; differential input for PMD receive or auto-MDIX transmit.
40	ANAGND4	power_in	Analog circuit ground connection; one of four analog ground pins.
41	LED_ACT/LED_COL/AN_EN_B	output	Port B Activity or Collision LED output; indicates activity in mode 1 or collision/duplex status in modes 2-3.
42	LED_SPEED_B/FXSD_B/AN1_B	output	Port B Speed indicator LED output; asserted high for 100 Mb/s operation and low for 10 Mb/s operation.
43	LED_LINK_B/AN0_B	output	Port B Link status LED output; indicates link presence (mode 1) or transmit/receive activity with link (modes 2-3).
44	PWRDOWN_INT_B	input	Port B Power Down/Interrupt control; active low input for power down mode or open-drain output for interrupt signaling.
45	TXD3_B/SNI_MODE_B	input	Port B MII Transmit Data bit 3; input sampled synchronously to TX_CLK_B (2.5 MHz to 25 MHz depending on mode).
46	TXD2_B	input	Port B MII Transmit Data bit 2; input sampled synchronously to TX_CLK_B (2.5 MHz to 25 MHz depending on mode).
47	TXD1_B	input	Port B MII Transmit Data bit 1; input sampled synchronously to TX_CLK_B (2.5 MHz to 25 MHz depending on mode).
48	TXD0_B	input	Port B MII Transmit Data bit 0; input sampled synchronously to TX_CLK_B (2.5 MHz to 25 MHz depending on mode).
49	TX_EN_B	input	Port B MII Transmit Enable input; active high indicates valid transmit data present on TXD[3:0]_B.
50	TX_CLK_B	output	Port B MII Transmit Clock output; 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, unused in RMII mode.
51	IOVDD2	power_in	I/O circuit 3.3V power supply; one of four I/O power supply pins for 3.3V logic.
52	IOGND2	power_in	I/O circuit ground connection; provides ground reference for 3.3V I/O logic.
53	RXD3_B/ED_EN_B	output	Port B MII Receive Data bit 3; driven synchronously to RX_CLK_B at 25 MHz (100 Mb/s) or 2.5 MHz (10 Mb/s) when RX_DV_B asserted.
54	PFBIN4	power_in	Power Feedback Input pin; fed with power from PFBOUT with 0.1µF bypass capacitor required.
55	COREGND2	power_in	Core circuit ground connection for internal logic circuits.
56	RXD2_B/EXTENDER_EN	output	Port B MII Receive Data bit 2; driven synchronously to RX_CLK_B at 25 MHz (100 Mb/s) or 2.5 MHz (10 Mb/s) when RX_DV_B asserted.
57	RXD1_B/PHYAD4	output	Port B MII Receive Data bit 1; driven synchronously to RX_CLK_B at 25 MHz (100 Mb/s) or 2.5 MHz (10 Mb/s) when RX_DV_B asserted.
58	RXD0_B/PHYAD3	output	Port B MII Receive Data bit 0; driven synchronously to RX_CLK_B at 25 MHz (100 Mb/s) or 2.5 MHz (10 Mb/s) when RX_DV_B asserted.
59	COL_B/FX_EN_B	output	Port B Collision Detect signal in half-duplex modes; asserted high for simultaneous transmit/receive activity or heartbeat.
60	RX_ER_B/MDIX_EN_B	output	Port B MII/RMII Receive Error indicator; asserted high to indicate invalid symbols in received packets or false carrier events.
61	CRS_B/CRS_DV_B/LED_CFG_B	output	Port B MII Carrier Sense or RMII Carrier Sense/Data Valid signal; asserted high when receive medium is non-idle.
62	RX_DV_B/MII_MODE_B	output	Port B MII Receive Data Valid signal; asserted high to indicate valid data is present on RXD[3:0]_B.
63	RX_CLK_B	output	Port B MII Receive Clock output; 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, unused in RMII mode.
64	IOGND3	power_in	I/O circuit ground connection; provides ground reference for 3.3V I/O logic.
65	IOVDD3	power_in	I/O circuit 3.3V power supply; one of four I/O power supply pins for 3.3V logic.
66	MDIO	bidirectional	Management Data I/O signal; bidirectional serial data line for register access via MDC clock, requires 1.5 kΩ pullup resistor.
67	MDC	input	Management Data Clock; synchronous clock for MDIO serial management interface with maximum clock rate of 25 MHz.
68	CLK2MAC	output	Clock to MAC output; provides 25 MHz reference clock in MII mode or 50 MHz in RMII mode for external devices.
69	X2	output	Crystal Oscillator output; connect to external 25 MHz crystal or leave unconnected if using external oscillator on X1.
70	X1	input	Crystal/Oscillator input; must be 25 MHz (±50 ppm) for MII mode or 50 MHz (±50 ppm) for RMII mode reference clock.
71	RESET_N	input	Active low Reset input; asserting low for minimum 1 µs initializes all internal registers and strap options to defaults.
72	TCK	input	JTAG Test Clock input; synchronous clock for boundary scan testing with weak internal pullup.
73	TDO	output	JTAG Test Data Output; serialized test data output for boundary scan device testing and verification.
74	TMS	input	JTAG Test Mode Select input; controls test state machine for boundary scan operations with weak internal pullup.
75	TRSTN	input	JTAG Test Reset input; active low to reset test state machine for JTAG operations with weak internal pullup.
76	TDI	input	JTAG Test Data Input; serialized test data input for boundary scan operations with weak internal pullup.
77	IOGND4	power_in	I/O circuit ground connection; provides ground reference for 3.3V I/O logic.
78	IOVDD4	power_in	I/O circuit 3.3V power supply; one of four I/O power supply pins for 3.3V logic.
79	RX_CLK_A	output	Port A MII Receive Clock output; 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, unused in RMII mode.
80	RX_DV_A/MII_MODE_A	output	Port A MII Receive Data Valid signal; asserted high to indicate valid data is present on RXD[3:0]_A.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TQFP-80(12x12)
Category	Logic
Pins	80

CAD (KiCad official)

Symbol: DP83849IFVS
Footprint: Package_QFP:TQFP-80_12x12mm_P0.5mm
3D model: TQFP-80(12x12) (KiCad packages3D, STEP)
3D model files: dp83849ifvs-etched.step / dp83849ifvs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83849ifvs.step / dp83849ifvs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (108 pp, sha256 9e32e105abdc3943, retrieved 2026-10-01, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF