component
DP83848TSQ
Public Made by Adomby adom
Texas Instruments Ethernet Transceivers, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+77@@ -0,0 +1,77 @@+# DP83848TSQ++**Texas Instruments** · Ethernet Transceivers · WQFN-40-EP(6x6)++DP83848TSQ from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | IOVDD33 | power_in | I/O 3.3-V Supply |+| 2 | TX_CLK | output | MII Transmit Clock output at 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode. |+| 3 | TX_EN | input | MII Transmit Enable active high input with internal pulldown indicating valid data on TXD[3:0]. |+| 4 | TXD_0 | input | MII Transmit Data bit 0 input synchronous to TX_CLK. |+| 5 | TXD_1 | input | MII Transmit Data bit 1 input synchronous to TX_CLK. |+| 6 | TXD_2 | input | MII Transmit Data bit 2 input synchronous to TX_CLK. |+| 7 | TXD_3 | input | MII Transmit Data bit 3 input with internal pulldown synchronous to TX_CLK. |+| 8 | RESERVED | unconnected | Reserved pin that must be left unconnected. |+| 9 | RESERVED | unconnected | Reserved pin that must be left unconnected. |+| 10 | RESERVED | unconnected | Reserved pin that must be left unconnected. |+| 11 | RD- | bidirectional | Differential receive input (PMD Input Pair) accepting 100BASE-TX or 10BASE-T signaling with 3.3-V bias requirement. |+| 12 | RD+ | bidirectional | Differential receive input (PMD Input Pair) accepting 100BASE-TX or 10BASE-T signaling with 3.3-V bias requirement. |+| 13 | AGND | power_in | Analog Ground connection. |+| 14 | TD- | bidirectional | Differential transmit output (PMD Output Pair) configured for 10BASE-T or 100BASE-TX with 3.3-V bias, can be RX pair in Auto-MDIX mode. |+| 15 | TD+ | bidirectional | Differential transmit output (PMD Output Pair) configured for 10BASE-T or 100BASE-TX with 3.3-V bias, can be RX pair in Auto-MDIX mode. |+| 16 | PFBIN1 | input | Power Feedback Input fed from PFBOUT pin requiring 0.1 µF capacitor placed close to pin. |+| 17 | AGND | power_in | Analog Ground connection. |+| 18 | AVDD33 | power_in | Analog 3.3-V Supply input. |+| 19 | PFBOUT | output | Power Feedback Output requiring 10 µF tantalum and 0.1 µF capacitors placed close to pin. |+| 20 | RBIAS | input | Bias Resistor Connection requiring 4.87-kΩ 1% resistor connected from this pin to GND. |+| 21 | CLK_OUT | output | 25-MHz Clock Output for DP83848T variant eliminating need for additional clock source component. |+| 22 | LED_LINK/AN0 | output | Link LED output with internal pullup indicating LINK status or strapping pin for Auto-Negotiation mode selection. |+| 23 | RESET_N | input | Active Low hardware reset input with internal pullup requiring minimum 1 µs pulse width to initialize device. |+| 24 | MDIO | bidirectional | Management Data I/O bi-directional management instruction/data signal requiring 1.5 kΩ external pullup resistor. |+| 25 | MDC | input | Management Data Clock synchronous clock to MDIO serial interface with maximum 25 MHz rate and no minimum rate. |+| 26 | IOVDD33 | power_in | I/O 3.3-V Supply input. |+| 27 | X2 | output | Crystal Output for external 25-MHz crystal resonator connection or left floating when CMOS oscillator is used. |+| 28 | X1 | input | Crystal/Oscillator Input for 25-MHz reference clock in MII mode or 50-MHz in RMII mode with 0.005% tolerance. |+| 29 | DGND | power_in | Digital Ground connection. |+| 30 | PFBIN2 | input | Power Feedback Input fed from PFBOUT pin requiring 0.1 µF capacitor placed close to pin. |+| 31 | RX_CLK | output | MII Receive Clock output at 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode, unused in RMII mode. |+| 32 | RX_DV/MII_MODE | output | MII Receive Data Valid output with internal pulldown asserted when valid data present, or MII Mode strapping pin (0=MII, 1=RMII). |+| 33 | CRS/CRS_DV/LED_CFG | output | MII Carrier Sense output with internal pullup asserted when receive medium non-idle, or LED Configuration strapping pin. |+| 34 | RX_ER/MDIX_EN | output | MII Receive Error output with internal pullup asserted high to indicate invalid symbol detected, or Auto-MDIX Enable strapping pin. |+| 35 | COL/PHYAD0 | output | MII Collision Detect output with internal pullup asserted for collision or heartbeat in half-duplex 10 Mb/s, or PHY Address bit 0 strapping pin. |+| 36 | RXD_0/PHYAD1 | output | MII Receive Data bit 0 with internal pulldown driven synchronously to RX_CLK, or PHY Address bit 1 strapping pin. |+| 37 | RXD_1/PHYAD2 | output | MII Receive Data bit 1 with internal pulldown driven synchronously to RX_CLK, or PHY Address bit 2 strapping pin. |+| 38 | RXD_2/PHYAD3 | output | MII Receive Data bit 2 with internal pulldown driven synchronously to RX_CLK, or PHY Address bit 3 strapping pin. |+| 39 | RXD_3/PHYAD4 | output | MII Receive Data bit 3 with internal pulldown driven synchronously to RX_CLK, or PHY Address bit 4 strapping pin. |+| 40 | IOGND | power_in | I/O Ground connection. |+| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-40-EP(6x6) |+| Category | Interface |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `DP83848TSQ`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `dp83848tsq-etched.step` / `dp83848tsq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83848tsq.step` / `dp83848tsq.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83848t) (87 pp, sha256 `942d2ded17c4be60`, retrieved 2026-09-26, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dp83848tsq-datasheet.pdf)
page.jsonadded+354@@ -0,0 +1,354 @@+{+ "slug": "dp83848tsq",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Ethernet Transceivers, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "dp83848tsq",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dp83848tsq.kicad_sym",+ "dp83848tsq.kicad_mod",+ "dp83848tsq.glb",+ "dp83848tsq.step",+ "dp83848tsq.lbr",+ "docs/hero.png",+ "docs/dp83848tsq-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DP83848TSQ",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-40-EP(6x6)",+ "pin_count": 41,+ "category": "Interface",+ "subcategory": "Ethernet Transceivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dp83848t",+ "parts": {+ "symbol": "dp83848tsq.kicad_sym",+ "footprint": "dp83848tsq.kicad_mod",+ "model_3d": "dp83848tsq-etched.glb",+ "model_3d_plain": "dp83848tsq.glb",+ "model_3d_step": "dp83848tsq-etched.step",+ "model_3d_step_plain": "dp83848tsq.step",+ "lbr": "dp83848tsq.lbr"+ },+ "distributor_links": {+ "lcsc": "C92110"+ },+ "distributor_check": {+ "checked_at": "2026-09-26T19:15:44Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "IOVDD33",+ "type": "power_in",+ "description": "I/O 3.3-V Supply"+ },+ {+ "number": "2",+ "name": "TX_CLK",+ "type": "output",+ "description": "MII Transmit Clock output at 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode."+ },+ {+ "number": "3",+ "name": "TX_EN",+ "type": "input",+ "description": "MII Transmit Enable active high input with internal pulldown indicating valid data on TXD[3:0]."+ },+ {+ "number": "4",+ "name": "TXD_0",+ "type": "input",+ "description": "MII Transmit Data bit 0 input synchronous to TX_CLK."+ },+ {+ "number": "5",+ "name": "TXD_1",+ "type": "input",+ "description": "MII Transmit Data bit 1 input synchronous to TX_CLK."+ },+ {+ "number": "6",+ "name": "TXD_2",+ "type": "input",+ "description": "MII Transmit Data bit 2 input synchronous to TX_CLK."+ },+ {+ "number": "7",+ "name": "TXD_3",+ "type": "input",+ "description": "MII Transmit Data bit 3 input with internal pulldown synchronous to TX_CLK."+ },+ {+ "number": "8",+ "name": "RESERVED",+ "type": "unconnected",+ "description": "Reserved pin that must be left unconnected."+ },+ {+ "number": "9",+ "name": "RESERVED",+ "type": "unconnected",+ "description": "Reserved pin that must be left unconnected."+ },+ {+ "number": "10",+ "name": "RESERVED",+ "type": "unconnected",+ "description": "Reserved pin that must be left unconnected."+ },+ {+ "number": "11",+ "name": "RD–",+ "type": "bidirectional",+ "description": "Differential receive input (PMD Input Pair) accepting 100BASE-TX or 10BASE-T signaling with 3.3-V bias requirement."+ },+ {+ "number": "12",+ "name": "RD+",+ "type": "bidirectional",+ "description": "Differential receive input (PMD Input Pair) accepting 100BASE-TX or 10BASE-T signaling with 3.3-V bias requirement."+ },+ {+ "number": "13",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground connection."+ },+ {+ "number": "14",+ "name": "TD-",+ "type": "bidirectional",+ "description": "Differential transmit output (PMD Output Pair) configured for 10BASE-T or 100BASE-TX with 3.3-V bias, can be RX pair in Auto-MDIX mode."+ },+ {+ "number": "15",+ "name": "TD+",+ "type": "bidirectional",+ "description": "Differential transmit output (PMD Output Pair) configured for 10BASE-T or 100BASE-TX with 3.3-V bias, can be RX pair in Auto-MDIX mode."+ },+ {+ "number": "16",+ "name": "PFBIN1",+ "type": "input",+ "description": "Power Feedback Input fed from PFBOUT pin requiring 0.1 µF capacitor placed close to pin."+ },+ {+ "number": "17",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog Ground connection."+ },+ {+ "number": "18",+ "name": "AVDD33",+ "type": "power_in",+ "description": "Analog 3.3-V Supply input."+ },+ {+ "number": "19",+ "name": "PFBOUT",+ "type": "output",+ "description": "Power Feedback Output requiring 10 µF tantalum and 0.1 µF capacitors placed close to pin."+ },+ {+ "number": "20",+ "name": "RBIAS",+ "type": "input",+ "description": "Bias Resistor Connection requiring 4.87-kΩ 1% resistor connected from this pin to GND."+ },+ {+ "number": "21",+ "name": "CLK_OUT",+ "type": "output",+ "description": "25-MHz Clock Output for DP83848T variant eliminating need for additional clock source component."+ },+ {+ "number": "22",+ "name": "LED_LINK/AN0",+ "type": "output",+ "description": "Link LED output with internal pullup indicating LINK status or strapping pin for Auto-Negotiation mode selection."+ },+ {+ "number": "23",+ "name": "RESET_N",+ "type": "input",+ "description": "Active Low hardware reset input with internal pullup requiring minimum 1 µs pulse width to initialize device."+ },+ {+ "number": "24",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Management Data I/O bi-directional management instruction/data signal requiring 1.5 kΩ external pullup resistor."+ },+ {+ "number": "25",+ "name": "MDC",+ "type": "input",+ "description": "Management Data Clock synchronous clock to MDIO serial interface with maximum 25 MHz rate and no minimum rate."+ },+ {+ "number": "26",+ "name": "IOVDD33",+ "type": "power_in",+ "description": "I/O 3.3-V Supply input."+ },+ {+ "number": "27",+ "name": "X2",+ "type": "output",+ "description": "Crystal Output for external 25-MHz crystal resonator connection or left floating when CMOS oscillator is used."+ },+ {+ "number": "28",+ "name": "X1",+ "type": "input",+ "description": "Crystal/Oscillator Input for 25-MHz reference clock in MII mode or 50-MHz in RMII mode with 0.005% tolerance."+ },+ {+ "number": "29",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital Ground connection."+ },+ {+ "number": "30",+ "name": "PFBIN2",+ "type": "input",+ "description": "Power Feedback Input fed from PFBOUT pin requiring 0.1 µF capacitor placed close to pin."+ },+ {+ "number": "31",+ "name": "RX_CLK",+ "type": "output",+ "description": "MII Receive Clock output at 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode, unused in RMII mode."+ },+ {+ "number": "32",+ "name": "RX_DV/MII_MODE",+ "type": "output",+ "description": "MII Receive Data Valid output with internal pulldown asserted when valid data present, or MII Mode strapping pin (0=MII, 1=RMII)."+ },+ {+ "number": "33",+ "name": "CRS/CRS_DV/LED_CFG",+ "type": "output",+ "description": "MII Carrier Sense output with internal pullup asserted when receive medium non-idle, or LED Configuration strapping pin."+ },+ {+ "number": "34",+ "name": "RX_ER/MDIX_EN",+ "type": "output",+ "description": "MII Receive Error output with internal pullup asserted high to indicate invalid symbol detected, or Auto-MDIX Enable strapping pin."+ },+ {+ "number": "35",+ "name": "COL/PHYAD0",+ "type": "output",+ "description": "MII Collision Detect output with internal pullup asserted for collision or heartbeat in half-duplex 10 Mb/s, or PHY Address bit 0 strapping pin."+ },+ {+ "number": "36",+ "name": "RXD_0/PHYAD1",+ "type": "output",+ "description": "MII Receive Data bit 0 with internal pulldown driven synchronously to RX_CLK, or PHY Address bit 1 strapping pin."+ },+ {+ "number": "37",+ "name": "RXD_1/PHYAD2",+ "type": "output",+ "description": "MII Receive Data bit 1 with internal pulldown driven synchronously to RX_CLK, or PHY Address bit 2 strapping pin."+ },+ {+ "number": "38",+ "name": "RXD_2/PHYAD3",+ "type": "output",+ "description": "MII Receive Data bit 2 with internal pulldown driven synchronously to RX_CLK, or PHY Address bit 3 strapping pin."+ },+ {+ "number": "39",+ "name": "RXD_3/PHYAD4",+ "type": "output",+ "description": "MII Receive Data bit 3 with internal pulldown driven synchronously to RX_CLK, or PHY Address bit 4 strapping pin."+ },+ {+ "number": "40",+ "name": "IOGND",+ "type": "power_in",+ "description": "I/O Ground connection."+ },+ {+ "number": "41",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: DP83848TSQ (T variant) has CLK_OUT on PIN 21 instead of LED_SPEED which appears on DP83848J/K varian; Multiple pins (22, 32, 33, 34, 35, 36, 37, 38, 39) function as both strapping options during reset a; PMD interface pins (11, 12, 14, 15) are bidirectional for auto-MDIX operation where RD± can transmit",+ "exposed pad 41 added from the footprint"+ ],+ "pages_sent": 87,+ "cost_usd": 0.7673,+ "at": "2026-09-26T19:15:24"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dp83848t",+ "pages": 87,+ "sha256": "942d2ded17c4be60",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}