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DP83848TSQ

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Texas Instruments Ethernet Transceivers, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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DP83848TSQ

Texas Instruments · Ethernet Transceivers · WQFN-40-EP(6x6)

DP83848TSQ from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IOVDD33 power_in I/O 3.3-V Supply
2 TX_CLK output MII Transmit Clock output at 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode.
3 TX_EN input MII Transmit Enable active high input with internal pulldown indicating valid data on TXD[3:0].
4 TXD_0 input MII Transmit Data bit 0 input synchronous to TX_CLK.
5 TXD_1 input MII Transmit Data bit 1 input synchronous to TX_CLK.
6 TXD_2 input MII Transmit Data bit 2 input synchronous to TX_CLK.
7 TXD_3 input MII Transmit Data bit 3 input with internal pulldown synchronous to TX_CLK.
8 RESERVED unconnected Reserved pin that must be left unconnected.
9 RESERVED unconnected Reserved pin that must be left unconnected.
10 RESERVED unconnected Reserved pin that must be left unconnected.
11 RD- bidirectional Differential receive input (PMD Input Pair) accepting 100BASE-TX or 10BASE-T signaling with 3.3-V bias requirement.
12 RD+ bidirectional Differential receive input (PMD Input Pair) accepting 100BASE-TX or 10BASE-T signaling with 3.3-V bias requirement.
13 AGND power_in Analog Ground connection.
14 TD- bidirectional Differential transmit output (PMD Output Pair) configured for 10BASE-T or 100BASE-TX with 3.3-V bias, can be RX pair in Auto-MDIX mode.
15 TD+ bidirectional Differential transmit output (PMD Output Pair) configured for 10BASE-T or 100BASE-TX with 3.3-V bias, can be RX pair in Auto-MDIX mode.
16 PFBIN1 input Power Feedback Input fed from PFBOUT pin requiring 0.1 µF capacitor placed close to pin.
17 AGND power_in Analog Ground connection.
18 AVDD33 power_in Analog 3.3-V Supply input.
19 PFBOUT output Power Feedback Output requiring 10 µF tantalum and 0.1 µF capacitors placed close to pin.
20 RBIAS input Bias Resistor Connection requiring 4.87-kΩ 1% resistor connected from this pin to GND.
21 CLK_OUT output 25-MHz Clock Output for DP83848T variant eliminating need for additional clock source component.
22 LED_LINK/AN0 output Link LED output with internal pullup indicating LINK status or strapping pin for Auto-Negotiation mode selection.
23 RESET_N input Active Low hardware reset input with internal pullup requiring minimum 1 µs pulse width to initialize device.
24 MDIO bidirectional Management Data I/O bi-directional management instruction/data signal requiring 1.5 kΩ external pullup resistor.
25 MDC input Management Data Clock synchronous clock to MDIO serial interface with maximum 25 MHz rate and no minimum rate.
26 IOVDD33 power_in I/O 3.3-V Supply input.
27 X2 output Crystal Output for external 25-MHz crystal resonator connection or left floating when CMOS oscillator is used.
28 X1 input Crystal/Oscillator Input for 25-MHz reference clock in MII mode or 50-MHz in RMII mode with 0.005% tolerance.
29 DGND power_in Digital Ground connection.
30 PFBIN2 input Power Feedback Input fed from PFBOUT pin requiring 0.1 µF capacitor placed close to pin.
31 RX_CLK output MII Receive Clock output at 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode, unused in RMII mode.
32 RX_DV/MII_MODE output MII Receive Data Valid output with internal pulldown asserted when valid data present, or MII Mode strapping pin (0=MII, 1=RMII).
33 CRS/CRS_DV/LED_CFG output MII Carrier Sense output with internal pullup asserted when receive medium non-idle, or LED Configuration strapping pin.
34 RX_ER/MDIX_EN output MII Receive Error output with internal pullup asserted high to indicate invalid symbol detected, or Auto-MDIX Enable strapping pin.
35 COL/PHYAD0 output MII Collision Detect output with internal pullup asserted for collision or heartbeat in half-duplex 10 Mb/s, or PHY Address bit 0 strapping pin.
36 RXD_0/PHYAD1 output MII Receive Data bit 0 with internal pulldown driven synchronously to RX_CLK, or PHY Address bit 1 strapping pin.
37 RXD_1/PHYAD2 output MII Receive Data bit 1 with internal pulldown driven synchronously to RX_CLK, or PHY Address bit 2 strapping pin.
38 RXD_2/PHYAD3 output MII Receive Data bit 2 with internal pulldown driven synchronously to RX_CLK, or PHY Address bit 3 strapping pin.
39 RXD_3/PHYAD4 output MII Receive Data bit 3 with internal pulldown driven synchronously to RX_CLK, or PHY Address bit 4 strapping pin.
40 IOGND power_in I/O Ground connection.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40-EP(6x6)
Category Interface
Pins 41

CAD (KiCad official)

  • Symbol: DP83848TSQ
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: dp83848tsq-etched.step / dp83848tsq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83848tsq.step / dp83848tsq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (87 pp, sha256 942d2ded17c4be60, retrieved 2026-09-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF