DP83848QSQX

Texas Instruments · Ethernet Transceivers · WQFN-40-EP(6x6)

DP83848QSQX from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IOVDD33	power_in	I/O 3.3-V supply; the recommended supply voltage is 3.3 V ± 0.3 V.
2	TX_CLK	output	MII transmit clock output at 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, derived from the 25 MHz reference; unused in RMII mode.
3	TX_EN	input	MII transmit enable: active-high input indicating valid data on TXD[3:0] (RMII: valid data on TXD[1:0]).
4	TXD_0	input	MII transmit data bit 0, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); in RMII mode, synchronous to the 50 MHz reference clock.
5	TXD_1	input	MII transmit data bit 1, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); in RMII mode, synchronous to the 50 MHz reference clock.
6	TXD_2	input	MII transmit data bit 2, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); not used in RMII mode.
7	TXD_3	input	MII transmit data bit 3, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); not used in RMII mode.
8	RESERVED	unconnected	Reserved pin that must be left unconnected.
9	RESERVED	unconnected	Reserved pin that must be left unconnected.
10	RESERVED	unconnected	Reserved pin that must be left unconnected.
11	RD-	bidirectional	Differential receive input (PMD input pair) auto-configured for 100BASE-TX or 10BASE-T; requires 3.3 V bias, and in Auto-MDIX mode may be used as the transmit output pair.
12	RD+	bidirectional	Differential receive input (PMD input pair) auto-configured for 100BASE-TX or 10BASE-T; requires 3.3 V bias, and in Auto-MDIX mode may be used as the transmit output pair.
13	AGND	power_in	Analog ground.
14	TD-	bidirectional	Differential transmit output (PMD output pair) automatically configured for 10BASE-T or 100BASE-TX; requires 3.3 V bias, and in Auto-MDIX mode may be used as the receive input pair.
15	TD+	bidirectional	Differential transmit output (PMD output pair) automatically configured for 10BASE-T or 100BASE-TX; requires 3.3 V bias, and in Auto-MDIX mode may be used as the receive input pair.
16	PFBIN1	input	Power feedback input fed only from PFBOUT, with a small 0.1 µF capacitor placed close to the pin; do not supply power to this pin from any other source.
17	AGND	power_in	Analog ground.
18	AVDD33	power_in	Analog 3.3-V supply.
19	PFBOUT	output	Power feedback output; parallel 10 µF (tantalum preferred) and 0.1 µF capacitors should be placed close to it, and it connects to PFBIN1 and PFBIN2.
20	RBIAS	input	Bias resistor connection: a 4.87 kΩ 1% resistor must be connected from RBIAS to GND.
21	CLK_OUT	output	System clock output: 25 MHz in MII mode and 50 MHz in RMII mode; in RMII mode the system clock output is not recommended as the MAC reference clock.
22	LED_LINK/AN0	bidirectional	LED_LINK output (ON when link is good; blinks on activity in Mode 2), which doubles as the AN0 strap sampled at hardware reset; it must never be connected directly to GND or VCC, and only a 2.2 kΩ resistor should be used.
23	RESET_N	input	Active-low reset input; asserting it low for at least 1 µs forces a reset that re-initializes all registers and re-latches the strap options.
24	MDIO	bidirectional	Management data I/O, bidirectional serial data for the station management interface; requires a 1.5 kΩ pull-up resistor.
25	MDC	input	Management data clock, synchronous to MDIO; maximum 25 MHz with no minimum clock rate.
26	IOVDD33	power_in	I/O 3.3-V supply; the recommended supply voltage is 3.3 V ± 0.3 V.
27	X2	output	Crystal output for an external 25 MHz crystal resonator; must be left unconnected when an external CMOS oscillator drives X1.
28	X1	input	Primary clock reference input, which must be a 25 MHz ±50 ppm clock source (crystal across X1/X2 or CMOS oscillator on X1); in RMII mode it is a 50 MHz ±50 ppm CMOS oscillator input.
29	DGND	power_in	Digital ground.
30	PFBIN2	input	Power feedback input fed only from PFBOUT, with a small 0.1 µF capacitor placed close to the pin; do not supply power to this pin from any other source.
31	RX_CLK	output	MII receive clock providing 25 MHz recovered clock for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode; unused in RMII mode.
32	RX_DV/MII_MODE	bidirectional	MII receive data valid (RMII: synchronous receive data valid), with MII_MODE strap where 0 selects MII and 1 selects RMII; the internal pull-down makes the default 0.
33	CRS/CRS_DV/LED_CFG	bidirectional	MII carrier sense (RMII: combined CRS/receive data valid), with LED_CFG strap selecting LED mode; the default is Mode 1 and the pin has an internal pull-up.
34	RX_ER/MDIX_EN	bidirectional	MII receive error output, with MDIX_EN strap where the default enables Auto-MDIX and an external pull-down disables it.
35	COL/PHYAD0	bidirectional	MII collision detect output, with PHYAD0 strap sampled at reset (weak internal pull-up).
36	RXD_0/PHYAD1	bidirectional	MII receive data bit 0 (RMII: RXD0), with PHYAD1 strap sampled at reset (weak internal pull-down).
37	RXD_1/PHYAD2	bidirectional	MII receive data bit 1 (RMII: RXD1), with PHYAD2 strap sampled at reset (weak internal pull-down).
38	RXD_2/PHYAD3	bidirectional	MII receive data bit 2, with PHYAD3 strap sampled at reset (weak internal pull-down).
39	RXD_3/PHYAD4	bidirectional	MII receive data bit 3, with PHYAD4 strap sampled at reset (weak internal pull-down).
40	IOGND	power_in	I/O ground.
41	DAP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-40-EP(6x6)
Category	Interface
Pins	41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VCC)	VCC	-0.5		4.2	V		11
DC Input Voltage (VIN)	VIN	-0.5			V		11
DC Output Voltage (VOUT)	VOUT	-0.5			V		11
Maximum Case Temperature				115	°C	for TA = 105°C	11
Maximum Die Temperature (TJ)	TJ			150	°C		11
Lead Temp. (TL) soldering	TL			260	°C	Soldering, 10 sec.	11
Storage temperature	Tstg	-65		150	°C		11
ESD Human body model (HBM)	V(ESD)	-4000		4000	V	HBM per AEC Q100-002, RZAP = 1.5k, CZAP = 100 pF	11
Supply voltage (VCC)	VCC	-0.3	3.3	0.3	V		11
Ambient Temperature (TA)	TA	-40		105	°C		11
Power Dissipation (PD)	PD			267	mW		11
Input High Voltage	VIH	2			V	Nominal VCC	12
Input Low Voltage	VIL			0.8	V		12
Input High Current	IIH			10	µA	VIN = VCC	12
Input Low Current	IIL			10	µA	VIN = GND	12
Output Low Voltage	VOL			0.4	V	IOL = 4 mA	12
TRI-STATE Leakage	IOZ	-10		10	µA	VOUT = VCC; VOUT = GND	12
100M Transmit Voltage	VTPTD_100	0.95	1	1.05	V	PMD Output Pair	12
100M Transmit Voltage Symmetry	VTPTDsym	-2		2	%	PMD Output Pair	12
10M Transmit Voltage	VTPTD_10	2.2	2.5	2.8	V	PMD Output Pair	12
Post Power Up Stabilization time prior to MDC preamble		167			ms	MDIO is pulled high for 32-bit serial management initialization	13
Hardware Configuration Latch-in Time from power up		167			ms	X1 clock must be stable for a min. of 167 ms at power up	13
MDC to MDIO (Output) Delay Time		0		30	ns		13
MDC Frequency		2.5		25	MHz		13
TX_CLK High/Low Time		16	20	24	ns	100 Mb/s Normal mode	13
RX_CLK High/Low Time		16	20	24	ns	100 Mb/s Normal mode	13
RX_CLK to RXD[3:0], RX_DV, RX_ER Delay		10		30	ns	100 Mb/s Normal mode	13
100 Mb/s PMD Output Pair tR and tF	tR and tF	3	4	5	ns		14
TX_CLK High/Low Time		190	200	210	ns	10 Mb/s MII mode	14
RX_CLK High/Low Time		160	200	240	ns	10 Mb/s MII mode	14
End of Packet High Time		250		300	ns	with '0' ending bit	14
Carrier Sense Turn On Delay (PMD Input Pair to CRS)		630		1000	ns	10BASE-T receive	14
RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising		2		14	ns		15
X1 to TX_CLK delay		0		5	ns	100 Mb/s Normal mode	16
Power Supply Current, 100BASE-TX (Full Duplex)	Idd100		81		mA	100BASE-TX (Full Duplex)	12
Power Supply Current, 10BASE-T (Full Duplex)	Idd10		92		mA	10BASE-T (Full Duplex)	12
Power Down Mode Supply Current	Idd		14		mA	CLK_OUT disabled	12
CMOS Input Capacitance	CIN1		5		pF		12
CMOS Output Capacitance	COUT1		5		pF		12
100BASE-TX Signal detect turn-on threshold	SDTHon		1000		mV diff pk-pk	PMD Input Pair	12
100BASE-TX Signal detect turn-off threshold	SDTHoff		200		mV diff pk-pk	PMD Input Pair	12
10BASE-T Receive Threshold	VTH1		585		mV	PMD Input Pair	12
Junction-to-ambient thermal resistance	RθJA		34.4		°C/W	RTA (WQFN) 40 pins	11
Junction-to-case (top) thermal resistance	RθJC(top)		21.1		°C/W	RTA (WQFN) 40 pins	11
Junction-to-board thermal resistance	RθJB		40.5		°C/W	RTA (WQFN) 40 pins	11
Junction-to-top characterization parameter	ψJT		0.4		°C/W	RTA (WQFN) 40 pins	11
Junction-to-board characterization parameter	ψJB		10.5		°C/W	RTA (WQFN) 40 pins	11
Junction-to-case (bottom) thermal resistance	RθJC(bot)		5.5		°C/W	RTA (WQFN) 40 pins	11
Hardware Configuration pins transition to output drivers			50		ns		13
Post RESET Stabilization time prior to MDC preamble			3		µs	MDIO is pulled high for 32-bit serial management initialization	13
Hardware Configuration Latch-in Time from the Deassertion of RESET			3		µs	either soft or hard reset	13
RESET pulse width			1		µs	X1 clock stable for min. of 1 µs during RESET pulse low time	13
X1 Clock Period (RMII transmit, 50 MHz reference)			20		ns	50 MHz Reference Clock	15
X1 Clock Period (RMII receive, 50 MHz reference)			20		ns	50 MHz Reference Clock	15
Isolation: software clear of BMCR bit 10 to Normal mode			100		µs	From software clear of bit 10 in the BMCR register	16
Isolation: deassertion of S/W or H/W reset to Normal mode			500		µs	From deassertion of S/W or H/W reset	16
SD Internal Turn-on Time			1		ms	100BASE-TX signal detect	15
SD Internal Turn-off Time			350		µs	100BASE-TX signal detect	15

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	abs		The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link pulse is nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data.	44

CAD (KiCad official)

Symbol: DP83848QSQX
Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
3D model files: dp83848qsqx-etched.step / dp83848qsqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83848qsqx.step / dp83848qsqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (86 pp, sha256 51891fdd0dd79df6, retrieved 2026-10-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# DP83848QSQX

**Texas Instruments** · Ethernet Transceivers · WQFN-40-EP(6x6)

DP83848QSQX from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IOVDD33 | power_in | I/O 3.3-V supply; the recommended supply voltage is 3.3 V ± 0.3 V. |
| 2 | TX_CLK | output | MII transmit clock output at 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, derived from the 25 MHz reference; unused in RMII mode. |
| 3 | TX_EN | input | MII transmit enable: active-high input indicating valid data on TXD[3:0] (RMII: valid data on TXD[1:0]). |
| 4 | TXD_0 | input | MII transmit data bit 0, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); in RMII mode, synchronous to the 50 MHz reference clock. |
| 5 | TXD_1 | input | MII transmit data bit 1, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); in RMII mode, synchronous to the 50 MHz reference clock. |
| 6 | TXD_2 | input | MII transmit data bit 2, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); not used in RMII mode. |
| 7 | TXD_3 | input | MII transmit data bit 3, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); not used in RMII mode. |
| 8 | RESERVED | unconnected | Reserved pin that must be left unconnected. |
| 9 | RESERVED | unconnected | Reserved pin that must be left unconnected. |
| 10 | RESERVED | unconnected | Reserved pin that must be left unconnected. |
| 11 | RD- | bidirectional | Differential receive input (PMD input pair) auto-configured for 100BASE-TX or 10BASE-T; requires 3.3 V bias, and in Auto-MDIX mode may be used as the transmit output pair. |
| 12 | RD+ | bidirectional | Differential receive input (PMD input pair) auto-configured for 100BASE-TX or 10BASE-T; requires 3.3 V bias, and in Auto-MDIX mode may be used as the transmit output pair. |
| 13 | AGND | power_in | Analog ground. |
| 14 | TD- | bidirectional | Differential transmit output (PMD output pair) automatically configured for 10BASE-T or 100BASE-TX; requires 3.3 V bias, and in Auto-MDIX mode may be used as the receive input pair. |
| 15 | TD+ | bidirectional | Differential transmit output (PMD output pair) automatically configured for 10BASE-T or 100BASE-TX; requires 3.3 V bias, and in Auto-MDIX mode may be used as the receive input pair. |
| 16 | PFBIN1 | input | Power feedback input fed only from PFBOUT, with a small 0.1 µF capacitor placed close to the pin; do not supply power to this pin from any other source. |
| 17 | AGND | power_in | Analog ground. |
| 18 | AVDD33 | power_in | Analog 3.3-V supply. |
| 19 | PFBOUT | output | Power feedback output; parallel 10 µF (tantalum preferred) and 0.1 µF capacitors should be placed close to it, and it connects to PFBIN1 and PFBIN2. |
| 20 | RBIAS | input | Bias resistor connection: a 4.87 kΩ 1% resistor must be connected from RBIAS to GND. |
| 21 | CLK_OUT | output | System clock output: 25 MHz in MII mode and 50 MHz in RMII mode; in RMII mode the system clock output is not recommended as the MAC reference clock. |
| 22 | LED_LINK/AN0 | bidirectional | LED_LINK output (ON when link is good; blinks on activity in Mode 2), which doubles as the AN0 strap sampled at hardware reset; it must never be connected directly to GND or VCC, and only a 2.2 kΩ resistor should be used. |
| 23 | RESET_N | input | Active-low reset input; asserting it low for at least 1 µs forces a reset that re-initializes all registers and re-latches the strap options. |
| 24 | MDIO | bidirectional | Management data I/O, bidirectional serial data for the station management interface; requires a 1.5 kΩ pull-up resistor. |
| 25 | MDC | input | Management data clock, synchronous to MDIO; maximum 25 MHz with no minimum clock rate. |
| 26 | IOVDD33 | power_in | I/O 3.3-V supply; the recommended supply voltage is 3.3 V ± 0.3 V. |
| 27 | X2 | output | Crystal output for an external 25 MHz crystal resonator; must be left unconnected when an external CMOS oscillator drives X1. |
| 28 | X1 | input | Primary clock reference input, which must be a 25 MHz ±50 ppm clock source (crystal across X1/X2 or CMOS oscillator on X1); in RMII mode it is a 50 MHz ±50 ppm CMOS oscillator input. |
| 29 | DGND | power_in | Digital ground. |
| 30 | PFBIN2 | input | Power feedback input fed only from PFBOUT, with a small 0.1 µF capacitor placed close to the pin; do not supply power to this pin from any other source. |
| 31 | RX_CLK | output | MII receive clock providing 25 MHz recovered clock for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode; unused in RMII mode. |
| 32 | RX_DV/MII_MODE | bidirectional | MII receive data valid (RMII: synchronous receive data valid), with MII_MODE strap where 0 selects MII and 1 selects RMII; the internal pull-down makes the default 0. |
| 33 | CRS/CRS_DV/LED_CFG | bidirectional | MII carrier sense (RMII: combined CRS/receive data valid), with LED_CFG strap selecting LED mode; the default is Mode 1 and the pin has an internal pull-up. |
| 34 | RX_ER/MDIX_EN | bidirectional | MII receive error output, with MDIX_EN strap where the default enables Auto-MDIX and an external pull-down disables it. |
| 35 | COL/PHYAD0 | bidirectional | MII collision detect output, with PHYAD0 strap sampled at reset (weak internal pull-up). |
| 36 | RXD_0/PHYAD1 | bidirectional | MII receive data bit 0 (RMII: RXD0), with PHYAD1 strap sampled at reset (weak internal pull-down). |
| 37 | RXD_1/PHYAD2 | bidirectional | MII receive data bit 1 (RMII: RXD1), with PHYAD2 strap sampled at reset (weak internal pull-down). |
| 38 | RXD_2/PHYAD3 | bidirectional | MII receive data bit 2, with PHYAD3 strap sampled at reset (weak internal pull-down). |
| 39 | RXD_3/PHYAD4 | bidirectional | MII receive data bit 3, with PHYAD4 strap sampled at reset (weak internal pull-down). |
| 40 | IOGND | power_in | I/O ground. |
| 41 | DAP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-40-EP(6x6) |
| Category | Interface |
| Pins | 41 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VCC) | VCC | -0.5 |  | 4.2 | V |  | 11 |
| DC Input Voltage (VIN) | VIN | -0.5 |  |  | V |  | 11 |
| DC Output Voltage (VOUT) | VOUT | -0.5 |  |  | V |  | 11 |
| Maximum Case Temperature |  |  |  | 115 | °C | for TA = 105°C | 11 |
| Maximum Die Temperature (TJ) | TJ |  |  | 150 | °C |  | 11 |
| Lead Temp. (TL) soldering | TL |  |  | 260 | °C | Soldering, 10 sec. | 11 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 11 |
| ESD Human body model (HBM) | V(ESD) | -4000 |  | 4000 | V | HBM per AEC Q100-002, RZAP = 1.5k, CZAP = 100 pF | 11 |
| Supply voltage (VCC) | VCC | -0.3 | 3.3 | 0.3 | V |  | 11 |
| Ambient Temperature (TA) | TA | -40 |  | 105 | °C |  | 11 |
| Power Dissipation (PD) | PD |  |  | 267 | mW |  | 11 |
| Input High Voltage | VIH | 2 |  |  | V | Nominal VCC | 12 |
| Input Low Voltage | VIL |  |  | 0.8 | V |  | 12 |
| Input High Current | IIH |  |  | 10 | µA | VIN = VCC | 12 |
| Input Low Current | IIL |  |  | 10 | µA | VIN = GND | 12 |
| Output Low Voltage | VOL |  |  | 0.4 | V | IOL = 4 mA | 12 |
| TRI-STATE Leakage | IOZ | -10 |  | 10 | µA | VOUT = VCC; VOUT = GND | 12 |
| 100M Transmit Voltage | VTPTD_100 | 0.95 | 1 | 1.05 | V | PMD Output Pair | 12 |
| 100M Transmit Voltage Symmetry | VTPTDsym | -2 |  | 2 | % | PMD Output Pair | 12 |
| 10M Transmit Voltage | VTPTD_10 | 2.2 | 2.5 | 2.8 | V | PMD Output Pair | 12 |
| Post Power Up Stabilization time prior to MDC preamble |  | 167 |  |  | ms | MDIO is pulled high for 32-bit serial management initialization | 13 |
| Hardware Configuration Latch-in Time from power up |  | 167 |  |  | ms | X1 clock must be stable for a min. of 167 ms at power up | 13 |
| MDC to MDIO (Output) Delay Time |  | 0 |  | 30 | ns |  | 13 |
| MDC Frequency |  | 2.5 |  | 25 | MHz |  | 13 |
| TX_CLK High/Low Time |  | 16 | 20 | 24 | ns | 100 Mb/s Normal mode | 13 |
| RX_CLK High/Low Time |  | 16 | 20 | 24 | ns | 100 Mb/s Normal mode | 13 |
| RX_CLK to RXD[3:0], RX_DV, RX_ER Delay |  | 10 |  | 30 | ns | 100 Mb/s Normal mode | 13 |
| 100 Mb/s PMD Output Pair tR and tF | tR and tF | 3 | 4 | 5 | ns |  | 14 |
| TX_CLK High/Low Time |  | 190 | 200 | 210 | ns | 10 Mb/s MII mode | 14 |
| RX_CLK High/Low Time |  | 160 | 200 | 240 | ns | 10 Mb/s MII mode | 14 |
| End of Packet High Time |  | 250 |  | 300 | ns | with '0' ending bit | 14 |
| Carrier Sense Turn On Delay (PMD Input Pair to CRS) |  | 630 |  | 1000 | ns | 10BASE-T receive | 14 |
| RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising |  | 2 |  | 14 | ns |  | 15 |
| X1 to TX_CLK delay |  | 0 |  | 5 | ns | 100 Mb/s Normal mode | 16 |
| Power Supply Current, 100BASE-TX (Full Duplex) | Idd100 |  | 81 |  | mA | 100BASE-TX (Full Duplex) | 12 |
| Power Supply Current, 10BASE-T (Full Duplex) | Idd10 |  | 92 |  | mA | 10BASE-T (Full Duplex) | 12 |
| Power Down Mode Supply Current | Idd |  | 14 |  | mA | CLK_OUT disabled | 12 |
| CMOS Input Capacitance | CIN1 |  | 5 |  | pF |  | 12 |
| CMOS Output Capacitance | COUT1 |  | 5 |  | pF |  | 12 |
| 100BASE-TX Signal detect turn-on threshold | SDTHon |  | 1000 |  | mV diff pk-pk | PMD Input Pair | 12 |
| 100BASE-TX Signal detect turn-off threshold | SDTHoff |  | 200 |  | mV diff pk-pk | PMD Input Pair | 12 |
| 10BASE-T Receive Threshold | VTH1 |  | 585 |  | mV | PMD Input Pair | 12 |
| Junction-to-ambient thermal resistance | RθJA |  | 34.4 |  | °C/W | RTA (WQFN) 40 pins | 11 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 21.1 |  | °C/W | RTA (WQFN) 40 pins | 11 |
| Junction-to-board thermal resistance | RθJB |  | 40.5 |  | °C/W | RTA (WQFN) 40 pins | 11 |
| Junction-to-top characterization parameter | ψJT |  | 0.4 |  | °C/W | RTA (WQFN) 40 pins | 11 |
| Junction-to-board characterization parameter | ψJB |  | 10.5 |  | °C/W | RTA (WQFN) 40 pins | 11 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 5.5 |  | °C/W | RTA (WQFN) 40 pins | 11 |
| Hardware Configuration pins transition to output drivers |  |  | 50 |  | ns |  | 13 |
| Post RESET Stabilization time prior to MDC preamble |  |  | 3 |  | µs | MDIO is pulled high for 32-bit serial management initialization | 13 |
| Hardware Configuration Latch-in Time from the Deassertion of RESET |  |  | 3 |  | µs | either soft or hard reset | 13 |
| RESET pulse width |  |  | 1 |  | µs | X1 clock stable for min. of 1 µs during RESET pulse low time | 13 |
| X1 Clock Period (RMII transmit, 50 MHz reference) |  |  | 20 |  | ns | 50 MHz Reference Clock | 15 |
| X1 Clock Period (RMII receive, 50 MHz reference) |  |  | 20 |  | ns | 50 MHz Reference Clock | 15 |
| Isolation: software clear of BMCR bit 10 to Normal mode |  |  | 100 |  | µs | From software clear of bit 10 in the BMCR register | 16 |
| Isolation: deassertion of S/W or H/W reset to Normal mode |  |  | 500 |  | µs | From deassertion of S/W or H/W reset | 16 |
| SD Internal Turn-on Time |  |  | 1 |  | ms | 100BASE-TX signal detect | 15 |
| SD Internal Turn-off Time |  |  | 350 |  | µs | 100BASE-TX signal detect | 15 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs |  | The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link pulse is nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data. | 44 |

## CAD (KiCad official)

- Symbol: `DP83848QSQX`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`
- 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `dp83848qsqx-etched.step` / `dp83848qsqx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83848qsqx.step` / `dp83848qsqx.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83848q-q1) (86 pp, sha256 `51891fdd0dd79df6`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dp83848qsqx-datasheet.pdf)