component
DP83848CVVX
Public Made by Adomby adom
Texas Instruments Ethernet Transceivers, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+84@@ -0,0 +1,84 @@+# DP83848CVVX++**Texas Instruments** · Ethernet Transceivers · LQFP-48(7x7)++DP83848CVVX from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TX_CLK | output | MII transmit clock: 25 MHz output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode; unused in RMII mode where X1 reference clock is used. |+| 2 | TX_EN | input | MII transmit enable: active high input with weak pulldown indicating presence of valid transmit data on TXD[3:0]. |+| 3 | TXD_0 | input | MII transmit data bit 0: accepts transmit data synchronous to TX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s). |+| 4 | TXD_1 | input | MII transmit data bit 1: accepts transmit data synchronous to TX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s). |+| 5 | TXD_2 | input | MII transmit data bit 2: accepts transmit data synchronous to TX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s). |+| 6 | TXD_3/SNI_MODE | input | MII transmit data bit 3 or SNI transmit data in serial mode; strapping pin for SNI_MODE configuration with weak pulldown. |+| 7 | PWR_DOWN/INT | input | Power down active low input (default) or open drain interrupt output when INT_OE bit set in MICR register; weak internal pullup. |+| 8 | TCK | input | JTAG test clock input for DP83848I/VYB/YB devices; weak internal pullup; DP83848C does not support JTAG. |+| 9 | TDO | output | JTAG test output for DP83848I/VYB/YB devices; DP83848C does not support JTAG. |+| 10 | TMS | input | JTAG test mode select input for DP83848I/VYB/YB devices; weak internal pullup; DP83848C does not support JTAG. |+| 11 | TRST# | input | JTAG test reset active low asynchronous input for DP83848I/VYB/YB devices; weak internal pullup; DP83848C does not support JTAG. |+| 12 | TDI | input | JTAG test data input for DP83848I/VYB/YB devices; weak internal pullup; DP83848C does not support JTAG. |+| 13 | RD- | input | Differential receive input pair (PMD Input Pair) for 10BASE-T or 100BASE-TX signaling; requires 3.3-V bias and can be used as transmit output in Auto-MDIX mode. |+| 14 | RD+ | input | Differential receive input pair (PMD Input Pair) for 10BASE-T or 100BASE-TX signaling; requires 3.3-V bias and can be used as transmit output in Auto-MDIX mode. |+| 15 | AGND | power_in | Analog ground connection for signal conditioning circuits. |+| 16 | TD- | output | Differential transmit output pair (PMD Output Pair) for 10BASE-T or 100BASE-TX signaling; requires 3.3-V bias and can be used as receive input in Auto-MDIX mode. |+| 17 | TD+ | output | Differential transmit output pair (PMD Output Pair) for 10BASE-T or 100BASE-TX signaling; requires 3.3-V bias and can be used as receive input in Auto-MDIX mode. |+| 18 | PFBIN1 | input | Power feedback input pin fed from PFBOUT; 0.1 µF capacitor should be placed close to this pin. |+| 19 | AGND | power_in | Analog ground connection for signal conditioning circuits. |+| 20 | RESERVED | unconnected | Reserved pin: must be pulled-up through 2.2 kΩ resistor to AVDD33 supply. |+| 21 | RESERVED | unconnected | Reserved pin: must be pulled-up through 2.2 kΩ resistor to AVDD33 supply. |+| 22 | AVDD33 | power_in | Analog 3.3-V power supply input. |+| 23 | PFBOUT | output | Power feedback output: parallel 10 µF (tantalum preferred) and 0.1 µF capacitors should be placed close to this pin and connected to PFBIN1 and PFBIN2. |+| 24 | RBIAS | input | Bias resistor connection: 4.87 kΩ 1% resistor should be connected from this pin to ground. |+| 25 | CLK_OUT | output | Clock output: provides 25 MHz output in MII mode or 50 MHz in RMII mode for use by external devices. |+| 26 | LED_ACT/COL/AN_EN | output | LED output for activity or collision indication, or duplex status in Mode 3; serves as AN_EN strapping pin for auto-negotiation enable with weak pullup. |+| 27 | LED_SPEED/AN1 | output | Speed LED output: on in 100 Mb/s, off in 10 Mb/s; serves as AN1 strapping pin for auto-negotiation mode selection. |+| 28 | LED_LINK/AN0 | output | Link LED output indicating link status or activity/blink depending on mode; serves as AN0 strapping pin for auto-negotiation with weak pullup. |+| 29 | RESET_N | input | Reset active low input: asserting low for minimum 1 µs forces device reset and re-initialization of all registers to default states; weak internal pullup. |+| 30 | MDIO | bidirectional | Management data I/O: bi-directional serial interface pin for register access; requires 1.5 kΩ external pullup resistor. |+| 31 | MDC | input | Management data clock: synchronous clock for MDIO serial interface with maximum clock rate of 25 MHz and no minimum rate. |+| 32 | IOVDD33 | power_in | I/O 3.3-V power supply input. |+| 33 | X2 | output | Crystal output: connect to 25 MHz external crystal resonator device; leave unconnected if using external CMOS oscillator. |+| 34 | X1 | input | Crystal/oscillator input: primary clock reference input for 25 MHz (MII mode) or 50 MHz (RMII mode) at 0.005% (±50 ppm); supports crystal or CMOS oscillator. |+| 35 | IOGND | power_in | I/O ground connection. |+| 36 | DGND | power_in | Digital ground connection. |+| 37 | PFBIN2 | input | Power feedback input pin fed from PFBOUT; 0.1 µF capacitor should be placed close to this pin. |+| 38 | RX_CLK | output | MII receive clock: provides 25 MHz recovered receive clock for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode; unused in RMII mode. |+| 39 | RX_DV/MII_MODE | output | MII receive data valid: asserted high to indicate valid data on RXD[3:0]; serves as MII_MODE strapping pin with weak pulldown for mode selection. |+| 40 | CRS/CRS_DV/LED_CFG | output | Carrier sense or CRS_DV in RMII mode: asserted high to indicate receive medium is non-idle; serves as LED_CFG strapping pin with weak pullup. |+| 41 | RX_ER/MDIX_EN | output | MII receive error: asserted high to indicate invalid symbol detection; serves as MDIX_EN strapping pin with weak pullup for auto-MDIX enable. |+| 42 | COL/PHYAD0 | output | Collision detect: asserted high for collision in half duplex or heartbeat in 10 Mb/s half duplex; serves as PHYAD0 (PHY address bit 0) strapping pin with weak pullup. |+| 43 | RXD_0/PHYAD1 | output | MII receive data bit 0: driven synchronously to RX_CLK with valid data when RX_DV asserted; serves as PHYAD1 strapping pin with weak pulldown. |+| 44 | RXD_1/PHYAD2 | output | MII receive data bit 1: driven synchronously to RX_CLK with valid data when RX_DV asserted; serves as PHYAD2 strapping pin with weak pulldown. |+| 45 | RXD_2/PHYAD3 | output | MII receive data bit 2: driven synchronously to RX_CLK with valid data when RX_DV asserted; serves as PHYAD3 strapping pin with weak pulldown. |+| 46 | RXD_3/PHYAD4 | output | MII receive data bit 3: driven synchronously to RX_CLK with valid data when RX_DV asserted; serves as PHYAD4 strapping pin with weak pulldown. |+| 47 | IOGND | power_in | I/O ground connection. |+| 48 | IOVDD33 | power_in | I/O 3.3-V power supply input. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-48(7x7) |+| Category | Interface |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `DP83848CVVX`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `dp83848cvvx-etched.step` / `dp83848cvvx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83848cvvx.step` / `dp83848cvvx.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83848c) (91 pp, sha256 `bf8147a3a31c031d`, retrieved 2026-09-26, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dp83848cvvx-datasheet.pdf)
page.jsonadded+395@@ -0,0 +1,395 @@+{+ "slug": "dp83848cvvx",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Ethernet Transceivers, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "dp83848cvvx",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dp83848cvvx.kicad_sym",+ "dp83848cvvx.kicad_mod",+ "dp83848cvvx.glb",+ "dp83848cvvx.step",+ "dp83848cvvx.lbr",+ "docs/hero.png",+ "docs/dp83848cvvx-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DP83848CVVX",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "Interface",+ "subcategory": "Ethernet Transceivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dp83848c",+ "parts": {+ "symbol": "dp83848cvvx.kicad_sym",+ "footprint": "dp83848cvvx.kicad_mod",+ "model_3d": "dp83848cvvx-etched.glb",+ "model_3d_plain": "dp83848cvvx.glb",+ "model_3d_step": "dp83848cvvx-etched.step",+ "model_3d_step_plain": "dp83848cvvx.step",+ "lbr": "dp83848cvvx.lbr"+ },+ "distributor_links": {+ "lcsc": "C16688"+ },+ "distributor_check": {+ "checked_at": "2026-09-26T13:58:12Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "TX_CLK",+ "type": "output",+ "description": "MII transmit clock: 25 MHz output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode; unused in RMII mode where X1 reference clock is used."+ },+ {+ "number": "2",+ "name": "TX_EN",+ "type": "input",+ "description": "MII transmit enable: active high input with weak pulldown indicating presence of valid transmit data on TXD[3:0]."+ },+ {+ "number": "3",+ "name": "TXD_0",+ "type": "input",+ "description": "MII transmit data bit 0: accepts transmit data synchronous to TX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s)."+ },+ {+ "number": "4",+ "name": "TXD_1",+ "type": "input",+ "description": "MII transmit data bit 1: accepts transmit data synchronous to TX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s)."+ },+ {+ "number": "5",+ "name": "TXD_2",+ "type": "input",+ "description": "MII transmit data bit 2: accepts transmit data synchronous to TX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s)."+ },+ {+ "number": "6",+ "name": "TXD_3/SNI_MODE",+ "type": "input",+ "description": "MII transmit data bit 3 or SNI transmit data in serial mode; strapping pin for SNI_MODE configuration with weak pulldown."+ },+ {+ "number": "7",+ "name": "PWR_DOWN/INT",+ "type": "input",+ "description": "Power down active low input (default) or open drain interrupt output when INT_OE bit set in MICR register; weak internal pullup."+ },+ {+ "number": "8",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock input for DP83848I/VYB/YB devices; weak internal pullup; DP83848C does not support JTAG."+ },+ {+ "number": "9",+ "name": "TDO",+ "type": "output",+ "description": "JTAG test output for DP83848I/VYB/YB devices; DP83848C does not support JTAG."+ },+ {+ "number": "10",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test mode select input for DP83848I/VYB/YB devices; weak internal pullup; DP83848C does not support JTAG."+ },+ {+ "number": "11",+ "name": "TRST#",+ "type": "input",+ "description": "JTAG test reset active low asynchronous input for DP83848I/VYB/YB devices; weak internal pullup; DP83848C does not support JTAG."+ },+ {+ "number": "12",+ "name": "TDI",+ "type": "input",+ "description": "JTAG test data input for DP83848I/VYB/YB devices; weak internal pullup; DP83848C does not support JTAG."+ },+ {+ "number": "13",+ "name": "RD-",+ "type": "input",+ "description": "Differential receive input pair (PMD Input Pair) for 10BASE-T or 100BASE-TX signaling; requires 3.3-V bias and can be used as transmit output in Auto-MDIX mode."+ },+ {+ "number": "14",+ "name": "RD+",+ "type": "input",+ "description": "Differential receive input pair (PMD Input Pair) for 10BASE-T or 100BASE-TX signaling; requires 3.3-V bias and can be used as transmit output in Auto-MDIX mode."+ },+ {+ "number": "15",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground connection for signal conditioning circuits."+ },+ {+ "number": "16",+ "name": "TD-",+ "type": "output",+ "description": "Differential transmit output pair (PMD Output Pair) for 10BASE-T or 100BASE-TX signaling; requires 3.3-V bias and can be used as receive input in Auto-MDIX mode."+ },+ {+ "number": "17",+ "name": "TD+",+ "type": "output",+ "description": "Differential transmit output pair (PMD Output Pair) for 10BASE-T or 100BASE-TX signaling; requires 3.3-V bias and can be used as receive input in Auto-MDIX mode."+ },+ {+ "number": "18",+ "name": "PFBIN1",+ "type": "input",+ "description": "Power feedback input pin fed from PFBOUT; 0.1 µF capacitor should be placed close to this pin."+ },+ {+ "number": "19",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground connection for signal conditioning circuits."+ },+ {+ "number": "20",+ "name": "RESERVED",+ "type": "unconnected",+ "description": "Reserved pin: must be pulled-up through 2.2 kΩ resistor to AVDD33 supply."+ },+ {+ "number": "21",+ "name": "RESERVED",+ "type": "unconnected",+ "description": "Reserved pin: must be pulled-up through 2.2 kΩ resistor to AVDD33 supply."+ },+ {+ "number": "22",+ "name": "AVDD33",+ "type": "power_in",+ "description": "Analog 3.3-V power supply input."+ },+ {+ "number": "23",+ "name": "PFBOUT",+ "type": "output",+ "description": "Power feedback output: parallel 10 µF (tantalum preferred) and 0.1 µF capacitors should be placed close to this pin and connected to PFBIN1 and PFBIN2."+ },+ {+ "number": "24",+ "name": "RBIAS",+ "type": "input",+ "description": "Bias resistor connection: 4.87 kΩ 1% resistor should be connected from this pin to ground."+ },+ {+ "number": "25",+ "name": "CLK_OUT",+ "type": "output",+ "description": "Clock output: provides 25 MHz output in MII mode or 50 MHz in RMII mode for use by external devices."+ },+ {+ "number": "26",+ "name": "LED_ACT/COL/AN_EN",+ "type": "output",+ "description": "LED output for activity or collision indication, or duplex status in Mode 3; serves as AN_EN strapping pin for auto-negotiation enable with weak pullup."+ },+ {+ "number": "27",+ "name": "LED_SPEED/AN1",+ "type": "output",+ "description": "Speed LED output: on in 100 Mb/s, off in 10 Mb/s; serves as AN1 strapping pin for auto-negotiation mode selection."+ },+ {+ "number": "28",+ "name": "LED_LINK/AN0",+ "type": "output",+ "description": "Link LED output indicating link status or activity/blink depending on mode; serves as AN0 strapping pin for auto-negotiation with weak pullup."+ },+ {+ "number": "29",+ "name": "RESET_N",+ "type": "input",+ "description": "Reset active low input: asserting low for minimum 1 µs forces device reset and re-initialization of all registers to default states; weak internal pullup."+ },+ {+ "number": "30",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Management data I/O: bi-directional serial interface pin for register access; requires 1.5 kΩ external pullup resistor."+ },+ {+ "number": "31",+ "name": "MDC",+ "type": "input",+ "description": "Management data clock: synchronous clock for MDIO serial interface with maximum clock rate of 25 MHz and no minimum rate."+ },+ {+ "number": "32",+ "name": "IOVDD33",+ "type": "power_in",+ "description": "I/O 3.3-V power supply input."+ },+ {+ "number": "33",+ "name": "X2",+ "type": "output",+ "description": "Crystal output: connect to 25 MHz external crystal resonator device; leave unconnected if using external CMOS oscillator."+ },+ {+ "number": "34",+ "name": "X1",+ "type": "input",+ "description": "Crystal/oscillator input: primary clock reference input for 25 MHz (MII mode) or 50 MHz (RMII mode) at 0.005% (±50 ppm); supports crystal or CMOS oscillator."+ },+ {+ "number": "35",+ "name": "IOGND",+ "type": "power_in",+ "description": "I/O ground connection."+ },+ {+ "number": "36",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground connection."+ },+ {+ "number": "37",+ "name": "PFBIN2",+ "type": "input",+ "description": "Power feedback input pin fed from PFBOUT; 0.1 µF capacitor should be placed close to this pin."+ },+ {+ "number": "38",+ "name": "RX_CLK",+ "type": "output",+ "description": "MII receive clock: provides 25 MHz recovered receive clock for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode; unused in RMII mode."+ },+ {+ "number": "39",+ "name": "RX_DV/MII_MODE",+ "type": "output",+ "description": "MII receive data valid: asserted high to indicate valid data on RXD[3:0]; serves as MII_MODE strapping pin with weak pulldown for mode selection."+ },+ {+ "number": "40",+ "name": "CRS/CRS_DV/LED_CFG",+ "type": "output",+ "description": "Carrier sense or CRS_DV in RMII mode: asserted high to indicate receive medium is non-idle; serves as LED_CFG strapping pin with weak pullup."+ },+ {+ "number": "41",+ "name": "RX_ER/MDIX_EN",+ "type": "output",+ "description": "MII receive error: asserted high to indicate invalid symbol detection; serves as MDIX_EN strapping pin with weak pullup for auto-MDIX enable."+ },+ {+ "number": "42",+ "name": "COL/PHYAD0",+ "type": "output",+ "description": "Collision detect: asserted high for collision in half duplex or heartbeat in 10 Mb/s half duplex; serves as PHYAD0 (PHY address bit 0) strapping pin with weak pullup."+ },+ {+ "number": "43",+ "name": "RXD_0/PHYAD1",+ "type": "output",+ "description": "MII receive data bit 0: driven synchronously to RX_CLK with valid data when RX_DV asserted; serves as PHYAD1 strapping pin with weak pulldown."+ },+ {+ "number": "44",+ "name": "RXD_1/PHYAD2",+ "type": "output",+ "description": "MII receive data bit 1: driven synchronously to RX_CLK with valid data when RX_DV asserted; serves as PHYAD2 strapping pin with weak pulldown."+ },+ {+ "number": "45",+ "name": "RXD_2/PHYAD3",+ "type": "output",+ "description": "MII receive data bit 2: driven synchronously to RX_CLK with valid data when RX_DV asserted; serves as PHYAD3 strapping pin with weak pulldown."+ },+ {+ "number": "46",+ "name": "RXD_3/PHYAD4",+ "type": "output",+ "description": "MII receive data bit 3: driven synchronously to RX_CLK with valid data when RX_DV asserted; serves as PHYAD4 strapping pin with weak pulldown."+ },+ {+ "number": "47",+ "name": "IOGND",+ "type": "power_in",+ "description": "I/O ground connection."+ },+ {+ "number": "48",+ "name": "IOVDD33",+ "type": "power_in",+ "description": "I/O 3.3-V power supply input."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: GNDPAD (thermal pad): Datasheet lists 49 items but LQFP-48 package specification shows 48 signal pin; Multiple pins serve dual/triple functions as both signal pins and strapping configuration pins (samp; PWR_DOWN/INT (pin 7): Multiplexed function configurable via MICR register bit 0 (INT_OE) - default i"+ ],+ "pages_sent": 91,+ "cost_usd": 1.1277,+ "at": "2026-09-26T13:57:48"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dp83848c",+ "pages": 91,+ "sha256": "bf8147a3a31c031d",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}