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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83848CVVX

Texas Instruments · Ethernet Transceivers · LQFP-48(7x7)

DP83848CVVX from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TX_CLK	output	MII transmit clock: 25 MHz output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode; unused in RMII mode where X1 reference clock is used.
2	TX_EN	input	MII transmit enable: active high input with weak pulldown indicating presence of valid transmit data on TXD[3:0].
3	TXD_0	input	MII transmit data bit 0: accepts transmit data synchronous to TX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s).
4	TXD_1	input	MII transmit data bit 1: accepts transmit data synchronous to TX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s).
5	TXD_2	input	MII transmit data bit 2: accepts transmit data synchronous to TX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s).
6	TXD_3/SNI_MODE	input	MII transmit data bit 3 or SNI transmit data in serial mode; strapping pin for SNI_MODE configuration with weak pulldown.
7	PWR_DOWN/INT	input	Power down active low input (default) or open drain interrupt output when INT_OE bit set in MICR register; weak internal pullup.
8	TCK	input	JTAG test clock input for DP83848I/VYB/YB devices; weak internal pullup; DP83848C does not support JTAG.
9	TDO	output	JTAG test output for DP83848I/VYB/YB devices; DP83848C does not support JTAG.
10	TMS	input	JTAG test mode select input for DP83848I/VYB/YB devices; weak internal pullup; DP83848C does not support JTAG.
11	TRST#	input	JTAG test reset active low asynchronous input for DP83848I/VYB/YB devices; weak internal pullup; DP83848C does not support JTAG.
12	TDI	input	JTAG test data input for DP83848I/VYB/YB devices; weak internal pullup; DP83848C does not support JTAG.
13	RD-	input	Differential receive input pair (PMD Input Pair) for 10BASE-T or 100BASE-TX signaling; requires 3.3-V bias and can be used as transmit output in Auto-MDIX mode.
14	RD+	input	Differential receive input pair (PMD Input Pair) for 10BASE-T or 100BASE-TX signaling; requires 3.3-V bias and can be used as transmit output in Auto-MDIX mode.
15	AGND	power_in	Analog ground connection for signal conditioning circuits.
16	TD-	output	Differential transmit output pair (PMD Output Pair) for 10BASE-T or 100BASE-TX signaling; requires 3.3-V bias and can be used as receive input in Auto-MDIX mode.
17	TD+	output	Differential transmit output pair (PMD Output Pair) for 10BASE-T or 100BASE-TX signaling; requires 3.3-V bias and can be used as receive input in Auto-MDIX mode.
18	PFBIN1	input	Power feedback input pin fed from PFBOUT; 0.1 µF capacitor should be placed close to this pin.
19	AGND	power_in	Analog ground connection for signal conditioning circuits.
20	RESERVED	unconnected	Reserved pin: must be pulled-up through 2.2 kΩ resistor to AVDD33 supply.
21	RESERVED	unconnected	Reserved pin: must be pulled-up through 2.2 kΩ resistor to AVDD33 supply.
22	AVDD33	power_in	Analog 3.3-V power supply input.
23	PFBOUT	output	Power feedback output: parallel 10 µF (tantalum preferred) and 0.1 µF capacitors should be placed close to this pin and connected to PFBIN1 and PFBIN2.
24	RBIAS	input	Bias resistor connection: 4.87 kΩ 1% resistor should be connected from this pin to ground.
25	CLK_OUT	output	Clock output: provides 25 MHz output in MII mode or 50 MHz in RMII mode for use by external devices.
26	LED_ACT/COL/AN_EN	output	LED output for activity or collision indication, or duplex status in Mode 3; serves as AN_EN strapping pin for auto-negotiation enable with weak pullup.
27	LED_SPEED/AN1	output	Speed LED output: on in 100 Mb/s, off in 10 Mb/s; serves as AN1 strapping pin for auto-negotiation mode selection.
28	LED_LINK/AN0	output	Link LED output indicating link status or activity/blink depending on mode; serves as AN0 strapping pin for auto-negotiation with weak pullup.
29	RESET_N	input	Reset active low input: asserting low for minimum 1 µs forces device reset and re-initialization of all registers to default states; weak internal pullup.
30	MDIO	bidirectional	Management data I/O: bi-directional serial interface pin for register access; requires 1.5 kΩ external pullup resistor.
31	MDC	input	Management data clock: synchronous clock for MDIO serial interface with maximum clock rate of 25 MHz and no minimum rate.
32	IOVDD33	power_in	I/O 3.3-V power supply input.
33	X2	output	Crystal output: connect to 25 MHz external crystal resonator device; leave unconnected if using external CMOS oscillator.
34	X1	input	Crystal/oscillator input: primary clock reference input for 25 MHz (MII mode) or 50 MHz (RMII mode) at 0.005% (±50 ppm); supports crystal or CMOS oscillator.
35	IOGND	power_in	I/O ground connection.
36	DGND	power_in	Digital ground connection.
37	PFBIN2	input	Power feedback input pin fed from PFBOUT; 0.1 µF capacitor should be placed close to this pin.
38	RX_CLK	output	MII receive clock: provides 25 MHz recovered receive clock for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode; unused in RMII mode.
39	RX_DV/MII_MODE	output	MII receive data valid: asserted high to indicate valid data on RXD[3:0]; serves as MII_MODE strapping pin with weak pulldown for mode selection.
40	CRS/CRS_DV/LED_CFG	output	Carrier sense or CRS_DV in RMII mode: asserted high to indicate receive medium is non-idle; serves as LED_CFG strapping pin with weak pullup.
41	RX_ER/MDIX_EN	output	MII receive error: asserted high to indicate invalid symbol detection; serves as MDIX_EN strapping pin with weak pullup for auto-MDIX enable.
42	COL/PHYAD0	output	Collision detect: asserted high for collision in half duplex or heartbeat in 10 Mb/s half duplex; serves as PHYAD0 (PHY address bit 0) strapping pin with weak pullup.
43	RXD_0/PHYAD1	output	MII receive data bit 0: driven synchronously to RX_CLK with valid data when RX_DV asserted; serves as PHYAD1 strapping pin with weak pulldown.
44	RXD_1/PHYAD2	output	MII receive data bit 1: driven synchronously to RX_CLK with valid data when RX_DV asserted; serves as PHYAD2 strapping pin with weak pulldown.
45	RXD_2/PHYAD3	output	MII receive data bit 2: driven synchronously to RX_CLK with valid data when RX_DV asserted; serves as PHYAD3 strapping pin with weak pulldown.
46	RXD_3/PHYAD4	output	MII receive data bit 3: driven synchronously to RX_CLK with valid data when RX_DV asserted; serves as PHYAD4 strapping pin with weak pulldown.
47	IOGND	power_in	I/O ground connection.
48	IOVDD33	power_in	I/O 3.3-V power supply input.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-48(7x7)
Category	Interface
Pins	48

CAD (KiCad official)

Symbol: DP83848CVVX
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: dp83848cvvx-etched.step / dp83848cvvx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83848cvvx.step / dp83848cvvx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (91 pp, sha256 bf8147a3a31c031d, retrieved 2026-09-26, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF