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DP83843BVJE

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Texas Instruments Ethernet Transceivers, QFP-80(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DP83843BVJE

Texas Instruments · Ethernet Transceivers · QFP-80(14x14)

DP83843BVJE from Texas Instruments, in a QFP-80(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RESET input Active-high input that initializes or reinitializes the DP83843; a positive pulse of at least 1 µs resets all registers to default and re-latches the strapping options.
2 NC unconnected No connect, reserved for future use; leave floating.
3 AN1 input Three-level input (1, M, 0) that works with AN0 to set the forced or advertised operating mode, latched at power-up, hardware or software reset.
4 AN0 input Three-level input (1, M, 0) that works with AN1 to set the forced or advertised operating mode, latched at power-up/reset.
5 SPEED10 output Indicates 10 Mb/s operation when high and 100 Mb/s operation when low; can drive peripheral circuitry such as an LED.
6 IO_VDD1 power_in TTL input/output supply #1, paired with IO_VSS1.
7 IO_VSS1 power_in TTL input/output ground #1, paired with IO_VDD1.
8 X2 output Crystal oscillator output for a 25 MHz crystal used with X1; must be left unconnected when an external CMOS oscillator drives X1.
9 X1 input Primary clock reference input, to be a 25 MHz 0.005% (50 ppm) source, either a crystal across X1/X2 or a CMOS oscillator on X1 only.
10 PCS_VDD power_in Physical Coding Sublayer supply, paired with PCS_VSS.
11 PCS_VSS power_in Physical Coding Sublayer ground, paired with PCS_VDD.
12 RXD[3] tri_state Nibble-wide receive data bit 3, synchronous to RX_CLK and driven on its falling edge; a don't care in 10 Mb/s serial mode.
13 RXD[2] tri_state Nibble-wide receive data bit 2, synchronous to RX_CLK and driven on its falling edge; a don't care in 10 Mb/s serial mode.
14 RXD[1] tri_state Nibble-wide receive data bit 1, synchronous to RX_CLK and driven on its falling edge; a don't care in 10 Mb/s serial mode.
15 RXD[0] tri_state Nibble-wide receive data bit 0; in 10 Mb/s serial mode it is the serial data output, clocked on the falling edge of RX_CLK.
16 IO_VDD2 power_in TTL input/output supply #2, paired with IO_VSS2.
17 IO_VSS2 power_in TTL input/output ground #2, paired with IO_VDD2.
18 RX_CLK tri_state Recovered receive clock: 25 MHz in 100 Mb/s mode, 2.5 MHz in 10 Mb/s nibble mode, and 10 MHz in 10 Mb/s serial mode.
19 RX_ER/RXD[4] tri_state Asserted high to indicate an invalid symbol in a received packet in 100 Mb/s mode; becomes RXD[4], the MSB of the receive 5-bit symbol, in Symbol mode.
20 RX_DV tri_state Asserted high to indicate valid data on RXD[3:0] (nibble mode) or RXD[0] (serial mode); driven on the falling edge of RX_CLK and not meaningful in Symbol mode.
21 COL/FXEN bidirectional COL asserts high to indicate collision in 10 and 100 Mb/s Half Duplex and is always 0 in Full Duplex; as FXEN it is an active-low strap (internal pull-up, pull low ~10 kΩ) that enables 100BASE-FX operation.
22 CRS/SYMBOL bidirectional CRS asserts high to indicate carrier presence in 10BASE-T or 100BASE-X Half Duplex; as SYMBOL it is an active-low strap (internal pull-up, pull low ~10 kΩ) that selects Symbol mode at 100 Mb/s.
23 RX_EN input Active-high enable for RXD[3:0], RX_CLK, RX_DV and RX_ER; a low places these outputs in TRI-STATE and it should be pulled high for node or switch operation.
24 TX_ER/TXD[4] input In 100 Mb/s mode, when high with TX_EN active the HALT symbol replaces the data nibble; ignored in 10 Mb/s mode, and TXD[4] (MSB of the transmit symbol) in Symbol mode.
25 TX_EN input Active-high input indicating valid nibble data on TXD[3:0] for 10 or 100 Mb/s nibble mode, or valid data on TXD[0] in 10 Mb/s serial mode.
26 IO_VDD3 power_in TTL input/output supply #3, paired with IO_VSS3.
27 IO_VSS3 power_in TTL input/output ground #3, paired with IO_VDD3.
28 TXD[3] input Nibble-wide MII transmit data bit 3, clocked at 2.5 MHz (10BASE-T) or 25 MHz (100BASE-X); ignored in 10 Mb/s serial mode.
29 TXD[2] input Nibble-wide MII transmit data bit 2, clocked at 2.5 MHz (10BASE-T) or 25 MHz (100BASE-X); ignored in 10 Mb/s serial mode.
30 TXD[1] input Nibble-wide MII transmit data bit 1, clocked at 2.5 MHz (10BASE-T) or 25 MHz (100BASE-X); ignored in 10 Mb/s serial mode.
31 TXD[0] input Nibble-wide MII transmit data bit 0; in 10 Mb/s serial mode it is the serial data input.
32 IO_VSS4 power_in TTL input/output ground #4; the datasheet lists no matching IO_VDD4 pin.
33 TX_CLK tri_state Transmit clock output: 25 MHz in 100BASE-TX, 2.5 MHz in 10BASE-T nibble mode, and 10 MHz in 10BASE-T serial mode.
34 MDIO bidirectional Bi-directional management instruction/data signal that requires a 1.5 kΩ pull-up resistor.
35 MDC input Management data clock synchronous to MDIO, with a maximum rate of 2.5 MHz and no minimum rate.
36 IO_VDD5 power_in TTL input/output supply #5, paired with IO_VSS5.
37 IO_VSS5 power_in TTL input/output ground #5, paired with IO_VDD5.
38 LED_FDPOL/PHYAD[4] bidirectional Full Duplex LED for 10 or 100 Mb/s operation (or 10BASE-T polarity indicator when configured); as PHYAD[4] it is strapped at power-up/reset with a pull-up/pull-down resistor (typically 10 kΩ).
39 LED_LINK/PHYAD[3] bidirectional Link LED indicating good link for 10 and 100 Mb/s operation; as PHYAD[3] it is strapped at power-up/reset with a pull-up/pull-down resistor (typically 10 kΩ).
40 LED_RX/PHYAD[2] bidirectional Receive LED indicating receive activity for 10 and 100 Mb/s operation with an approximately 50 ms monostable; as PHYAD[2] it is strapped at power-up/reset.
41 LED_TX/PHYAD[1] bidirectional Transmit LED indicating transmit activity for 10 and 100 Mb/s operation with an approximately 50 ms monostable; as PHYAD[1] it is strapped at power-up/reset.
42 LED_COL/PHYAD[0] bidirectional Collision LED indicating collision activity in 10 and 100 Mb/s Half Duplex operation; as PHYAD[0] it is strapped at power-up/reset.
43 FXTD+/AUITD+ output Differential output driving 125 Mb/s PECL for 100BASE-FX or AUI Manchester data at 10 Mb/s; enabled only in 100BASE-FX configuration.
44 FXTD-/AUITD- output Complementary differential output driving 125 Mb/s PECL for 100BASE-FX or AUI Manchester data at 10 Mb/s; enabled only in 100BASE-FX configuration.
45 AUIFX_GND power_in AUI power supply ground, paired with AUIFX_VDD.
46 AUIFX_VDD power_in AUI power supply, paired with AUIFX_GND.
47 FXSD-/CD- input Complementary 125 Mb/s PECL signal-detect input for 100BASE-FX or complementary AUI collision-detect input at 10 Mb/s.
48 FXSD+/CD+ input Differential 125 Mb/s PECL signal-detect input for 100BASE-FX or AUI collision-detect input at 10 Mb/s.
49 FXRD-/AUIRD- input Complementary 125 Mb/s PECL receive input for 100BASE-FX or AUI Manchester receive input at 10 Mb/s; enabled only in 100BASE-FX configuration.
50 FXRD+/AUIRD+ input Differential 125 Mb/s PECL receive input for 100BASE-FX or AUI Manchester receive input at 10 Mb/s; enabled only in 100BASE-FX configuration.
51 CP_AGND power_in CRM/CGM supply ground, paired with CP_AVDD.
52 CP_AVDD power_in CRM/CGM supply, paired with CP_AGND.
53 CPTW_DVSS power_in CRM/CGM digital ground, paired with CPTW_DVDD.
54 CPTW_DVDD power_in CRM/CGM digital supply, paired with CPTW_DVSS.
55 NC unconnected No connect, reserved for future use; leave floating.
56 NC unconnected No connect, reserved for future use; leave floating.
57 ATP_GND power_in 100BASE-T PMD supply ground.
58 NC unconnected No connect, reserved for future use; leave floating.
59 NC unconnected No connect, reserved for future use; leave floating.
60 TWREF input External reference resistor to TW_AGND that sets TP-PMD receiver equalization; the value is 70k ±1%.
61 BGREF input External current reference resistor for the internal bandgap circuitry; the value is 4.87k ±1%.
62 NC unconnected No connect, reserved for future use; leave floating.
63 THIN/REPEATER bidirectional THIN controls an external CTI coaxial transceiver via bit 3 of register 18h; as REPEATER, high selects 100 Mb/s repeater mode and low selects node mode, latched at power-up/reset (internal pull-up, pull low ~10 kΩ for node).
64 TW_AGND power_in 100 Mb/s power supply ground, paired with TW_AVDD.
65 TPRD- input Complementary differential receive input accepting 10BASE-T or 100BASE-TX scrambled MLT-3 data, automatically configured.
66 VCM_CAP passive Common mode bypass capacitor connection for receive filtering; a 0.0033 µF capacitor in parallel with a 0.10 µF capacitor is recommended.
67 TPRD+ input Differential receive input accepting 10BASE-T or 100BASE-TX scrambled MLT-3 data, automatically configured.
68 TW_AVDD power_in 100 Mb/s power supply, paired with TW_AGND.
69 SERIAL10 input Active-low select for 10 Mb/s serial MII on TXD[0]/RXD[0] at a 10 MHz clock; internal pull-up, latched at reset, and ignored at 100 Mb/s.
70 SUB_GND1 power_in 100BASE-T PMD substrate ground.
71 CD_GND0 power_in Common driver ground, paired with CD_VDD0.
72 CD_VDD0 power_in Common driver supply, paired with CD_GND0.
73 TPTD- output Complementary differential transmit output for 10BASE-T or 100BASE-TX MLT-3 signaling, configured automatically.
74 TPTD+ output Differential transmit output for 10BASE-T or 100BASE-TX MLT-3 signaling, configured automatically.
75 CD_GND1 power_in Common driver ground, paired with CD_VDD1.
76 CD_VDD1 power_in Common driver supply, paired with CD_GND1.
77 SUB_GND2 power_in 100BASE-T PMD substrate ground.
78 TXAR100 passive Transmit amplitude reference pin; a resistor to ground or VCC adjusts the 100BASE-TX amplitude toward 2 V pk-pk differential ±5%, and the pin may float in typical applications.
79 TR_AVDD power_in 10 Mb/s supply, paired with TR_AGND.
80 TR_AGND power_in 10 Mb/s supply ground, paired with TR_AVDD.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFP-80(14x14)
Category Interface
Pins 80

CAD (KiCad official)

  • Symbol: DP83843BVJE
  • Footprint: Package_QFP:LQFP-80_14x14mm_P0.65mm
  • 3D model: QFP-80(14x14) (KiCad packages3D, STEP)
  • 3D model files: dp83843bvje-etched.step / dp83843bvje-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83843bvje.step / dp83843bvje.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (91 pp, sha256 375dfba8351a3cf9, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF