component
DP83843BVJE
Public Made by Adomby adom
Texas Instruments Ethernet Transceivers, QFP-80(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+116@@ -0,0 +1,116 @@+# DP83843BVJE++**Texas Instruments** · Ethernet Transceivers · QFP-80(14x14)++DP83843BVJE from Texas Instruments, in a QFP-80(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RESET | input | Active-high input that initializes or reinitializes the DP83843; a positive pulse of at least 1 µs resets all registers to default and re-latches the strapping options. |+| 2 | NC | unconnected | No connect, reserved for future use; leave floating. |+| 3 | AN1 | input | Three-level input (1, M, 0) that works with AN0 to set the forced or advertised operating mode, latched at power-up, hardware or software reset. |+| 4 | AN0 | input | Three-level input (1, M, 0) that works with AN1 to set the forced or advertised operating mode, latched at power-up/reset. |+| 5 | SPEED10 | output | Indicates 10 Mb/s operation when high and 100 Mb/s operation when low; can drive peripheral circuitry such as an LED. |+| 6 | IO_VDD1 | power_in | TTL input/output supply #1, paired with IO_VSS1. |+| 7 | IO_VSS1 | power_in | TTL input/output ground #1, paired with IO_VDD1. |+| 8 | X2 | output | Crystal oscillator output for a 25 MHz crystal used with X1; must be left unconnected when an external CMOS oscillator drives X1. |+| 9 | X1 | input | Primary clock reference input, to be a 25 MHz 0.005% (50 ppm) source, either a crystal across X1/X2 or a CMOS oscillator on X1 only. |+| 10 | PCS_VDD | power_in | Physical Coding Sublayer supply, paired with PCS_VSS. |+| 11 | PCS_VSS | power_in | Physical Coding Sublayer ground, paired with PCS_VDD. |+| 12 | RXD[3] | tri_state | Nibble-wide receive data bit 3, synchronous to RX_CLK and driven on its falling edge; a don't care in 10 Mb/s serial mode. |+| 13 | RXD[2] | tri_state | Nibble-wide receive data bit 2, synchronous to RX_CLK and driven on its falling edge; a don't care in 10 Mb/s serial mode. |+| 14 | RXD[1] | tri_state | Nibble-wide receive data bit 1, synchronous to RX_CLK and driven on its falling edge; a don't care in 10 Mb/s serial mode. |+| 15 | RXD[0] | tri_state | Nibble-wide receive data bit 0; in 10 Mb/s serial mode it is the serial data output, clocked on the falling edge of RX_CLK. |+| 16 | IO_VDD2 | power_in | TTL input/output supply #2, paired with IO_VSS2. |+| 17 | IO_VSS2 | power_in | TTL input/output ground #2, paired with IO_VDD2. |+| 18 | RX_CLK | tri_state | Recovered receive clock: 25 MHz in 100 Mb/s mode, 2.5 MHz in 10 Mb/s nibble mode, and 10 MHz in 10 Mb/s serial mode. |+| 19 | RX_ER/RXD[4] | tri_state | Asserted high to indicate an invalid symbol in a received packet in 100 Mb/s mode; becomes RXD[4], the MSB of the receive 5-bit symbol, in Symbol mode. |+| 20 | RX_DV | tri_state | Asserted high to indicate valid data on RXD[3:0] (nibble mode) or RXD[0] (serial mode); driven on the falling edge of RX_CLK and not meaningful in Symbol mode. |+| 21 | COL/FXEN | bidirectional | COL asserts high to indicate collision in 10 and 100 Mb/s Half Duplex and is always 0 in Full Duplex; as FXEN it is an active-low strap (internal pull-up, pull low ~10 kΩ) that enables 100BASE-FX operation. |+| 22 | CRS/SYMBOL | bidirectional | CRS asserts high to indicate carrier presence in 10BASE-T or 100BASE-X Half Duplex; as SYMBOL it is an active-low strap (internal pull-up, pull low ~10 kΩ) that selects Symbol mode at 100 Mb/s. |+| 23 | RX_EN | input | Active-high enable for RXD[3:0], RX_CLK, RX_DV and RX_ER; a low places these outputs in TRI-STATE and it should be pulled high for node or switch operation. |+| 24 | TX_ER/TXD[4] | input | In 100 Mb/s mode, when high with TX_EN active the HALT symbol replaces the data nibble; ignored in 10 Mb/s mode, and TXD[4] (MSB of the transmit symbol) in Symbol mode. |+| 25 | TX_EN | input | Active-high input indicating valid nibble data on TXD[3:0] for 10 or 100 Mb/s nibble mode, or valid data on TXD[0] in 10 Mb/s serial mode. |+| 26 | IO_VDD3 | power_in | TTL input/output supply #3, paired with IO_VSS3. |+| 27 | IO_VSS3 | power_in | TTL input/output ground #3, paired with IO_VDD3. |+| 28 | TXD[3] | input | Nibble-wide MII transmit data bit 3, clocked at 2.5 MHz (10BASE-T) or 25 MHz (100BASE-X); ignored in 10 Mb/s serial mode. |+| 29 | TXD[2] | input | Nibble-wide MII transmit data bit 2, clocked at 2.5 MHz (10BASE-T) or 25 MHz (100BASE-X); ignored in 10 Mb/s serial mode. |+| 30 | TXD[1] | input | Nibble-wide MII transmit data bit 1, clocked at 2.5 MHz (10BASE-T) or 25 MHz (100BASE-X); ignored in 10 Mb/s serial mode. |+| 31 | TXD[0] | input | Nibble-wide MII transmit data bit 0; in 10 Mb/s serial mode it is the serial data input. |+| 32 | IO_VSS4 | power_in | TTL input/output ground #4; the datasheet lists no matching IO_VDD4 pin. |+| 33 | TX_CLK | tri_state | Transmit clock output: 25 MHz in 100BASE-TX, 2.5 MHz in 10BASE-T nibble mode, and 10 MHz in 10BASE-T serial mode. |+| 34 | MDIO | bidirectional | Bi-directional management instruction/data signal that requires a 1.5 kΩ pull-up resistor. |+| 35 | MDC | input | Management data clock synchronous to MDIO, with a maximum rate of 2.5 MHz and no minimum rate. |+| 36 | IO_VDD5 | power_in | TTL input/output supply #5, paired with IO_VSS5. |+| 37 | IO_VSS5 | power_in | TTL input/output ground #5, paired with IO_VDD5. |+| 38 | LED_FDPOL/PHYAD[4] | bidirectional | Full Duplex LED for 10 or 100 Mb/s operation (or 10BASE-T polarity indicator when configured); as PHYAD[4] it is strapped at power-up/reset with a pull-up/pull-down resistor (typically 10 kΩ). |+| 39 | LED_LINK/PHYAD[3] | bidirectional | Link LED indicating good link for 10 and 100 Mb/s operation; as PHYAD[3] it is strapped at power-up/reset with a pull-up/pull-down resistor (typically 10 kΩ). |+| 40 | LED_RX/PHYAD[2] | bidirectional | Receive LED indicating receive activity for 10 and 100 Mb/s operation with an approximately 50 ms monostable; as PHYAD[2] it is strapped at power-up/reset. |+| 41 | LED_TX/PHYAD[1] | bidirectional | Transmit LED indicating transmit activity for 10 and 100 Mb/s operation with an approximately 50 ms monostable; as PHYAD[1] it is strapped at power-up/reset. |+| 42 | LED_COL/PHYAD[0] | bidirectional | Collision LED indicating collision activity in 10 and 100 Mb/s Half Duplex operation; as PHYAD[0] it is strapped at power-up/reset. |+| 43 | FXTD+/AUITD+ | output | Differential output driving 125 Mb/s PECL for 100BASE-FX or AUI Manchester data at 10 Mb/s; enabled only in 100BASE-FX configuration. |+| 44 | FXTD-/AUITD- | output | Complementary differential output driving 125 Mb/s PECL for 100BASE-FX or AUI Manchester data at 10 Mb/s; enabled only in 100BASE-FX configuration. |+| 45 | AUIFX_GND | power_in | AUI power supply ground, paired with AUIFX_VDD. |+| 46 | AUIFX_VDD | power_in | AUI power supply, paired with AUIFX_GND. |+| 47 | FXSD-/CD- | input | Complementary 125 Mb/s PECL signal-detect input for 100BASE-FX or complementary AUI collision-detect input at 10 Mb/s. |+| 48 | FXSD+/CD+ | input | Differential 125 Mb/s PECL signal-detect input for 100BASE-FX or AUI collision-detect input at 10 Mb/s. |+| 49 | FXRD-/AUIRD- | input | Complementary 125 Mb/s PECL receive input for 100BASE-FX or AUI Manchester receive input at 10 Mb/s; enabled only in 100BASE-FX configuration. |+| 50 | FXRD+/AUIRD+ | input | Differential 125 Mb/s PECL receive input for 100BASE-FX or AUI Manchester receive input at 10 Mb/s; enabled only in 100BASE-FX configuration. |+| 51 | CP_AGND | power_in | CRM/CGM supply ground, paired with CP_AVDD. |+| 52 | CP_AVDD | power_in | CRM/CGM supply, paired with CP_AGND. |+| 53 | CPTW_DVSS | power_in | CRM/CGM digital ground, paired with CPTW_DVDD. |+| 54 | CPTW_DVDD | power_in | CRM/CGM digital supply, paired with CPTW_DVSS. |+| 55 | NC | unconnected | No connect, reserved for future use; leave floating. |+| 56 | NC | unconnected | No connect, reserved for future use; leave floating. |+| 57 | ATP_GND | power_in | 100BASE-T PMD supply ground. |+| 58 | NC | unconnected | No connect, reserved for future use; leave floating. |+| 59 | NC | unconnected | No connect, reserved for future use; leave floating. |+| 60 | TWREF | input | External reference resistor to TW_AGND that sets TP-PMD receiver equalization; the value is 70k ±1%. |+| 61 | BGREF | input | External current reference resistor for the internal bandgap circuitry; the value is 4.87k ±1%. |+| 62 | NC | unconnected | No connect, reserved for future use; leave floating. |+| 63 | THIN/REPEATER | bidirectional | THIN controls an external CTI coaxial transceiver via bit 3 of register 18h; as REPEATER, high selects 100 Mb/s repeater mode and low selects node mode, latched at power-up/reset (internal pull-up, pull low ~10 kΩ for node). |+| 64 | TW_AGND | power_in | 100 Mb/s power supply ground, paired with TW_AVDD. |+| 65 | TPRD- | input | Complementary differential receive input accepting 10BASE-T or 100BASE-TX scrambled MLT-3 data, automatically configured. |+| 66 | VCM_CAP | passive | Common mode bypass capacitor connection for receive filtering; a 0.0033 µF capacitor in parallel with a 0.10 µF capacitor is recommended. |+| 67 | TPRD+ | input | Differential receive input accepting 10BASE-T or 100BASE-TX scrambled MLT-3 data, automatically configured. |+| 68 | TW_AVDD | power_in | 100 Mb/s power supply, paired with TW_AGND. |+| 69 | SERIAL10 | input | Active-low select for 10 Mb/s serial MII on TXD[0]/RXD[0] at a 10 MHz clock; internal pull-up, latched at reset, and ignored at 100 Mb/s. |+| 70 | SUB_GND1 | power_in | 100BASE-T PMD substrate ground. |+| 71 | CD_GND0 | power_in | Common driver ground, paired with CD_VDD0. |+| 72 | CD_VDD0 | power_in | Common driver supply, paired with CD_GND0. |+| 73 | TPTD- | output | Complementary differential transmit output for 10BASE-T or 100BASE-TX MLT-3 signaling, configured automatically. |+| 74 | TPTD+ | output | Differential transmit output for 10BASE-T or 100BASE-TX MLT-3 signaling, configured automatically. |+| 75 | CD_GND1 | power_in | Common driver ground, paired with CD_VDD1. |+| 76 | CD_VDD1 | power_in | Common driver supply, paired with CD_GND1. |+| 77 | SUB_GND2 | power_in | 100BASE-T PMD substrate ground. |+| 78 | TXAR100 | passive | Transmit amplitude reference pin; a resistor to ground or VCC adjusts the 100BASE-TX amplitude toward 2 V pk-pk differential ±5%, and the pin may float in typical applications. |+| 79 | TR_AVDD | power_in | 10 Mb/s supply, paired with TR_AGND. |+| 80 | TR_AGND | power_in | 10 Mb/s supply ground, paired with TR_AVDD. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | QFP-80(14x14) |+| Category | Interface |+| Pins | 80 |++## CAD (KiCad official)++- Symbol: `DP83843BVJE`+- Footprint: `Package_QFP:LQFP-80_14x14mm_P0.65mm`+- 3D model: QFP-80(14x14) (KiCad packages3D, STEP)+- 3D model files: `dp83843bvje-etched.step` / `dp83843bvje-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83843bvje.step` / `dp83843bvje.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83843) (91 pp, sha256 `375dfba8351a3cf9`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dp83843bvje-datasheet.pdf)
page.jsonadded+633@@ -0,0 +1,633 @@+{+ "slug": "dp83843bvje",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Ethernet Transceivers, QFP-80(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "dp83843bvje",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dp83843bvje.kicad_sym",+ "dp83843bvje.kicad_mod",+ "dp83843bvje.glb",+ "dp83843bvje.step",+ "dp83843bvje.lbr",+ "docs/hero.png",+ "docs/dp83843bvje-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "dp83843bvje-hero.glb",+ "dp83843bvje-hero.overlay.json"+ ],+ "component": {+ "mpn": "DP83843BVJE",+ "manufacturer": "Texas Instruments",+ "package": "QFP-80(14x14)",+ "pin_count": 80,+ "category": "Interface",+ "subcategory": "Ethernet Transceivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dp83843",+ "parts": {+ "symbol": "dp83843bvje.kicad_sym",+ "footprint": "dp83843bvje.kicad_mod",+ "model_3d": "dp83843bvje-hero.glb",+ "model_3d_plain": "dp83843bvje.glb",+ "model_3d_step": "dp83843bvje-etched.step",+ "model_3d_step_plain": "dp83843bvje.step",+ "lbr": "dp83843bvje.lbr"+ },+ "distributor_links": {+ "lcsc": "C2872531",+ "digikey": "2156-DP83843BVJE-TI-ND",+ "mouser": "926-DP83843BVJE"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T17:07:14Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "2156-DP83843BVJE-TI-ND",+ "status": "found",+ "lifecycle": "Not For New Designs"+ },+ "mouser": {+ "pn": "926-DP83843BVJE",+ "status": "found",+ "lifecycle": "Obsolete"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "RESET",+ "type": "input",+ "description": "Active-high input that initializes or reinitializes the DP83843; a positive pulse of at least 1 µs resets all registers to default and re-latches the strapping options."+ },+ {+ "number": "2",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect, reserved for future use; leave floating."+ },+ {+ "number": "3",+ "name": "AN1",+ "type": "input",+ "description": "Three-level input (1, M, 0) that works with AN0 to set the forced or advertised operating mode, latched at power-up, hardware or software reset."+ },+ {+ "number": "4",+ "name": "AN0",+ "type": "input",+ "description": "Three-level input (1, M, 0) that works with AN1 to set the forced or advertised operating mode, latched at power-up/reset."+ },+ {+ "number": "5",+ "name": "SPEED10",+ "type": "output",+ "description": "Indicates 10 Mb/s operation when high and 100 Mb/s operation when low; can drive peripheral circuitry such as an LED."+ },+ {+ "number": "6",+ "name": "IO_VDD1",+ "type": "power_in",+ "description": "TTL input/output supply #1, paired with IO_VSS1."+ },+ {+ "number": "7",+ "name": "IO_VSS1",+ "type": "power_in",+ "description": "TTL input/output ground #1, paired with IO_VDD1."+ },+ {+ "number": "8",+ "name": "X2",+ "type": "output",+ "description": "Crystal oscillator output for a 25 MHz crystal used with X1; must be left unconnected when an external CMOS oscillator drives X1."+ },+ {+ "number": "9",+ "name": "X1",+ "type": "input",+ "description": "Primary clock reference input, to be a 25 MHz 0.005% (50 ppm) source, either a crystal across X1/X2 or a CMOS oscillator on X1 only."+ },+ {+ "number": "10",+ "name": "PCS_VDD",+ "type": "power_in",+ "description": "Physical Coding Sublayer supply, paired with PCS_VSS."+ },+ {+ "number": "11",+ "name": "PCS_VSS",+ "type": "power_in",+ "description": "Physical Coding Sublayer ground, paired with PCS_VDD."+ },+ {+ "number": "12",+ "name": "RXD[3]",+ "type": "tri_state",+ "description": "Nibble-wide receive data bit 3, synchronous to RX_CLK and driven on its falling edge; a don't care in 10 Mb/s serial mode."+ },+ {+ "number": "13",+ "name": "RXD[2]",+ "type": "tri_state",+ "description": "Nibble-wide receive data bit 2, synchronous to RX_CLK and driven on its falling edge; a don't care in 10 Mb/s serial mode."+ },+ {+ "number": "14",+ "name": "RXD[1]",+ "type": "tri_state",+ "description": "Nibble-wide receive data bit 1, synchronous to RX_CLK and driven on its falling edge; a don't care in 10 Mb/s serial mode."+ },+ {+ "number": "15",+ "name": "RXD[0]",+ "type": "tri_state",+ "description": "Nibble-wide receive data bit 0; in 10 Mb/s serial mode it is the serial data output, clocked on the falling edge of RX_CLK."+ },+ {+ "number": "16",+ "name": "IO_VDD2",+ "type": "power_in",+ "description": "TTL input/output supply #2, paired with IO_VSS2."+ },+ {+ "number": "17",+ "name": "IO_VSS2",+ "type": "power_in",+ "description": "TTL input/output ground #2, paired with IO_VDD2."+ },+ {+ "number": "18",+ "name": "RX_CLK",+ "type": "tri_state",+ "description": "Recovered receive clock: 25 MHz in 100 Mb/s mode, 2.5 MHz in 10 Mb/s nibble mode, and 10 MHz in 10 Mb/s serial mode."+ },+ {+ "number": "19",+ "name": "RX_ER/RXD[4]",+ "type": "tri_state",+ "description": "Asserted high to indicate an invalid symbol in a received packet in 100 Mb/s mode; becomes RXD[4], the MSB of the receive 5-bit symbol, in Symbol mode."+ },+ {+ "number": "20",+ "name": "RX_DV",+ "type": "tri_state",+ "description": "Asserted high to indicate valid data on RXD[3:0] (nibble mode) or RXD[0] (serial mode); driven on the falling edge of RX_CLK and not meaningful in Symbol mode."+ },+ {+ "number": "21",+ "name": "COL/FXEN",+ "type": "bidirectional",+ "description": "COL asserts high to indicate collision in 10 and 100 Mb/s Half Duplex and is always 0 in Full Duplex; as FXEN it is an active-low strap (internal pull-up, pull low ~10 kΩ) that enables 100BASE-FX operation."+ },+ {+ "number": "22",+ "name": "CRS/SYMBOL",+ "type": "bidirectional",+ "description": "CRS asserts high to indicate carrier presence in 10BASE-T or 100BASE-X Half Duplex; as SYMBOL it is an active-low strap (internal pull-up, pull low ~10 kΩ) that selects Symbol mode at 100 Mb/s."+ },+ {+ "number": "23",+ "name": "RX_EN",+ "type": "input",+ "description": "Active-high enable for RXD[3:0], RX_CLK, RX_DV and RX_ER; a low places these outputs in TRI-STATE and it should be pulled high for node or switch operation."+ },+ {+ "number": "24",+ "name": "TX_ER/TXD[4]",+ "type": "input",+ "description": "In 100 Mb/s mode, when high with TX_EN active the HALT symbol replaces the data nibble; ignored in 10 Mb/s mode, and TXD[4] (MSB of the transmit symbol) in Symbol mode."+ },+ {+ "number": "25",+ "name": "TX_EN",+ "type": "input",+ "description": "Active-high input indicating valid nibble data on TXD[3:0] for 10 or 100 Mb/s nibble mode, or valid data on TXD[0] in 10 Mb/s serial mode."+ },+ {+ "number": "26",+ "name": "IO_VDD3",+ "type": "power_in",+ "description": "TTL input/output supply #3, paired with IO_VSS3."+ },+ {+ "number": "27",+ "name": "IO_VSS3",+ "type": "power_in",+ "description": "TTL input/output ground #3, paired with IO_VDD3."+ },+ {+ "number": "28",+ "name": "TXD[3]",+ "type": "input",+ "description": "Nibble-wide MII transmit data bit 3, clocked at 2.5 MHz (10BASE-T) or 25 MHz (100BASE-X); ignored in 10 Mb/s serial mode."+ },+ {+ "number": "29",+ "name": "TXD[2]",+ "type": "input",+ "description": "Nibble-wide MII transmit data bit 2, clocked at 2.5 MHz (10BASE-T) or 25 MHz (100BASE-X); ignored in 10 Mb/s serial mode."+ },+ {+ "number": "30",+ "name": "TXD[1]",+ "type": "input",+ "description": "Nibble-wide MII transmit data bit 1, clocked at 2.5 MHz (10BASE-T) or 25 MHz (100BASE-X); ignored in 10 Mb/s serial mode."+ },+ {+ "number": "31",+ "name": "TXD[0]",+ "type": "input",+ "description": "Nibble-wide MII transmit data bit 0; in 10 Mb/s serial mode it is the serial data input."+ },+ {+ "number": "32",+ "name": "IO_VSS4",+ "type": "power_in",+ "description": "TTL input/output ground #4; the datasheet lists no matching IO_VDD4 pin."+ },+ {+ "number": "33",+ "name": "TX_CLK",+ "type": "tri_state",+ "description": "Transmit clock output: 25 MHz in 100BASE-TX, 2.5 MHz in 10BASE-T nibble mode, and 10 MHz in 10BASE-T serial mode."+ },+ {+ "number": "34",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Bi-directional management instruction/data signal that requires a 1.5 kΩ pull-up resistor."+ },+ {+ "number": "35",+ "name": "MDC",+ "type": "input",+ "description": "Management data clock synchronous to MDIO, with a maximum rate of 2.5 MHz and no minimum rate."+ },+ {+ "number": "36",+ "name": "IO_VDD5",+ "type": "power_in",+ "description": "TTL input/output supply #5, paired with IO_VSS5."+ },+ {+ "number": "37",+ "name": "IO_VSS5",+ "type": "power_in",+ "description": "TTL input/output ground #5, paired with IO_VDD5."+ },+ {+ "number": "38",+ "name": "LED_FDPOL/PHYAD[4]",+ "type": "bidirectional",+ "description": "Full Duplex LED for 10 or 100 Mb/s operation (or 10BASE-T polarity indicator when configured); as PHYAD[4] it is strapped at power-up/reset with a pull-up/pull-down resistor (typically 10 kΩ)."+ },+ {+ "number": "39",+ "name": "LED_LINK/PHYAD[3]",+ "type": "bidirectional",+ "description": "Link LED indicating good link for 10 and 100 Mb/s operation; as PHYAD[3] it is strapped at power-up/reset with a pull-up/pull-down resistor (typically 10 kΩ)."+ },+ {+ "number": "40",+ "name": "LED_RX/PHYAD[2]",+ "type": "bidirectional",+ "description": "Receive LED indicating receive activity for 10 and 100 Mb/s operation with an approximately 50 ms monostable; as PHYAD[2] it is strapped at power-up/reset."+ },+ {+ "number": "41",+ "name": "LED_TX/PHYAD[1]",+ "type": "bidirectional",+ "description": "Transmit LED indicating transmit activity for 10 and 100 Mb/s operation with an approximately 50 ms monostable; as PHYAD[1] it is strapped at power-up/reset."+ },+ {+ "number": "42",+ "name": "LED_COL/PHYAD[0]",+ "type": "bidirectional",+ "description": "Collision LED indicating collision activity in 10 and 100 Mb/s Half Duplex operation; as PHYAD[0] it is strapped at power-up/reset."+ },+ {+ "number": "43",+ "name": "FXTD+/AUITD+",+ "type": "output",+ "description": "Differential output driving 125 Mb/s PECL for 100BASE-FX or AUI Manchester data at 10 Mb/s; enabled only in 100BASE-FX configuration."+ },+ {+ "number": "44",+ "name": "FXTD-/AUITD-",+ "type": "output",+ "description": "Complementary differential output driving 125 Mb/s PECL for 100BASE-FX or AUI Manchester data at 10 Mb/s; enabled only in 100BASE-FX configuration."+ },+ {+ "number": "45",+ "name": "AUIFX_GND",+ "type": "power_in",+ "description": "AUI power supply ground, paired with AUIFX_VDD."+ },+ {+ "number": "46",+ "name": "AUIFX_VDD",+ "type": "power_in",+ "description": "AUI power supply, paired with AUIFX_GND."+ },+ {+ "number": "47",+ "name": "FXSD-/CD-",+ "type": "input",+ "description": "Complementary 125 Mb/s PECL signal-detect input for 100BASE-FX or complementary AUI collision-detect input at 10 Mb/s."+ },+ {+ "number": "48",+ "name": "FXSD+/CD+",+ "type": "input",+ "description": "Differential 125 Mb/s PECL signal-detect input for 100BASE-FX or AUI collision-detect input at 10 Mb/s."+ },+ {+ "number": "49",+ "name": "FXRD-/AUIRD-",+ "type": "input",+ "description": "Complementary 125 Mb/s PECL receive input for 100BASE-FX or AUI Manchester receive input at 10 Mb/s; enabled only in 100BASE-FX configuration."+ },+ {+ "number": "50",+ "name": "FXRD+/AUIRD+",+ "type": "input",+ "description": "Differential 125 Mb/s PECL receive input for 100BASE-FX or AUI Manchester receive input at 10 Mb/s; enabled only in 100BASE-FX configuration."+ },+ {+ "number": "51",+ "name": "CP_AGND",+ "type": "power_in",+ "description": "CRM/CGM supply ground, paired with CP_AVDD."+ },+ {+ "number": "52",+ "name": "CP_AVDD",+ "type": "power_in",+ "description": "CRM/CGM supply, paired with CP_AGND."+ },+ {+ "number": "53",+ "name": "CPTW_DVSS",+ "type": "power_in",+ "description": "CRM/CGM digital ground, paired with CPTW_DVDD."+ },+ {+ "number": "54",+ "name": "CPTW_DVDD",+ "type": "power_in",+ "description": "CRM/CGM digital supply, paired with CPTW_DVSS."+ },+ {+ "number": "55",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect, reserved for future use; leave floating."+ },+ {+ "number": "56",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect, reserved for future use; leave floating."+ },+ {+ "number": "57",+ "name": "ATP_GND",+ "type": "power_in",+ "description": "100BASE-T PMD supply ground."+ },+ {+ "number": "58",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect, reserved for future use; leave floating."+ },+ {+ "number": "59",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect, reserved for future use; leave floating."+ },+ {+ "number": "60",+ "name": "TWREF",+ "type": "input",+ "description": "External reference resistor to TW_AGND that sets TP-PMD receiver equalization; the value is 70k ±1%."+ },+ {+ "number": "61",+ "name": "BGREF",+ "type": "input",+ "description": "External current reference resistor for the internal bandgap circuitry; the value is 4.87k ±1%."+ },+ {+ "number": "62",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect, reserved for future use; leave floating."+ },+ {+ "number": "63",+ "name": "THIN/REPEATER",+ "type": "bidirectional",+ "description": "THIN controls an external CTI coaxial transceiver via bit 3 of register 18h; as REPEATER, high selects 100 Mb/s repeater mode and low selects node mode, latched at power-up/reset (internal pull-up, pull low ~10 kΩ for node)."+ },+ {+ "number": "64",+ "name": "TW_AGND",+ "type": "power_in",+ "description": "100 Mb/s power supply ground, paired with TW_AVDD."+ },+ {+ "number": "65",+ "name": "TPRD-",+ "type": "input",+ "description": "Complementary differential receive input accepting 10BASE-T or 100BASE-TX scrambled MLT-3 data, automatically configured."+ },+ {+ "number": "66",+ "name": "VCM_CAP",+ "type": "passive",+ "description": "Common mode bypass capacitor connection for receive filtering; a 0.0033 µF capacitor in parallel with a 0.10 µF capacitor is recommended."+ },+ {+ "number": "67",+ "name": "TPRD+",+ "type": "input",+ "description": "Differential receive input accepting 10BASE-T or 100BASE-TX scrambled MLT-3 data, automatically configured."+ },+ {+ "number": "68",+ "name": "TW_AVDD",+ "type": "power_in",+ "description": "100 Mb/s power supply, paired with TW_AGND."+ },+ {+ "number": "69",+ "name": "SERIAL10",+ "type": "input",+ "description": "Active-low select for 10 Mb/s serial MII on TXD[0]/RXD[0] at a 10 MHz clock; internal pull-up, latched at reset, and ignored at 100 Mb/s."+ },+ {+ "number": "70",+ "name": "SUB_GND1",+ "type": "power_in",+ "description": "100BASE-T PMD substrate ground."+ },+ {+ "number": "71",+ "name": "CD_GND0",+ "type": "power_in",+ "description": "Common driver ground, paired with CD_VDD0."+ },+ {+ "number": "72",+ "name": "CD_VDD0",+ "type": "power_in",+ "description": "Common driver supply, paired with CD_GND0."+ },+ {+ "number": "73",+ "name": "TPTD-",+ "type": "output",+ "description": "Complementary differential transmit output for 10BASE-T or 100BASE-TX MLT-3 signaling, configured automatically."+ },+ {+ "number": "74",+ "name": "TPTD+",+ "type": "output",+ "description": "Differential transmit output for 10BASE-T or 100BASE-TX MLT-3 signaling, configured automatically."+ },+ {+ "number": "75",+ "name": "CD_GND1",+ "type": "power_in",+ "description": "Common driver ground, paired with CD_VDD1."+ },+ {+ "number": "76",+ "name": "CD_VDD1",+ "type": "power_in",+ "description": "Common driver supply, paired with CD_GND1."+ },+ {+ "number": "77",+ "name": "SUB_GND2",+ "type": "power_in",+ "description": "100BASE-T PMD substrate ground."+ },+ {+ "number": "78",+ "name": "TXAR100",+ "type": "passive",+ "description": "Transmit amplitude reference pin; a resistor to ground or VCC adjusts the 100BASE-TX amplitude toward 2 V pk-pk differential ±5%, and the pin may float in typical applications."+ },+ {+ "number": "79",+ "name": "TR_AVDD",+ "type": "power_in",+ "description": "10 Mb/s supply, paired with TR_AGND."+ },+ {+ "number": "80",+ "name": "TR_AGND",+ "type": "power_in",+ "description": "10 Mb/s supply ground, paired with TR_AVDD."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package is taken from the datasheet's VJE80 (NS) and TI NNC QFP 80-pin entries. The 14x14 mm body si; The datasheet lists SUB_GND1 and SUB_GND2 together on pins 70 and 77 without stating which is which.; IO_VSS4 is on pin 32 but there is no IO_VDD4 in the datasheet pin list. This is reported as printed."+ ],+ "pages_sent": 22,+ "cost_usd": 0.1842,+ "at": "2026-10-08T17:06:38"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dp83843",+ "pages": 91,+ "sha256": "375dfba8351a3cf9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 80,+ "described": 80,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "dp83843bvje.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 16.4,+ 16.4,+ 1.6+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "477979184005b1973cf4f2ae93e03c5a50342504190416921945164d4f1db58d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "dp83843bvje-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 16.4,+ 16.4,+ 1.6+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "5d1a2557cd209628b7a422195565652615aa0dd67eedb3ec724432caaf178cd9",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}