component
DP83826IRHBT
Public Made by Adomby adom
Texas Instruments Ethernet Controllers, VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
Publish 0.1.0
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{
"slug": "dp83826irhbt",
"version": "0.1.0",
"type": "component",
"description": "Texas Instruments Ethernet Controllers, VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"interface",
"dp83826irhbt",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
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"path": "docs/hero.png"
},
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"README.md",
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"dp83826irhbt.kicad_mod",
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"dp83826irhbt.step",
"dp83826irhbt.lbr",
"docs/hero.png",
"docs/dp83826irhbt-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"dp83826irhbt-hero.glb",
"dp83826irhbt-hero.overlay.json",
"dp83826irhbt-etched.glb"
],
"component": {
"mpn": "DP83826IRHBT",
"manufacturer": "Texas Instruments",
"package": "VQFN-32(5x5)",
"pin_count": 33,
"category": "Interface",
"subcategory": "Ethernet Controllers",
"datasheet": "https://www.ti.com/lit/ds/symlink/dp83826i.pdf",
"parts": {
"symbol": "dp83826irhbt.kicad_sym",
"footprint": "dp83826irhbt.kicad_mod",
"model_3d": "dp83826irhbt-hero.glb",
"model_3d_plain": "dp83826irhbt-etched.glb",
"model_3d_step": "dp83826irhbt-etched.step",
"model_3d_step_plain": "dp83826irhbt.step",
"lbr": "dp83826irhbt.lbr"
},
"distributor_links": {
"lcsc": "C3225659",
"digikey": "296-DP83826IRHBTTR-ND",
"mouser": "595-DP83826IRHBT"
},
"distributor_check": {
"checked_at": "2026-11-06T02:15:42Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "296-DP83826IRHBTTR-ND",
"status": "found"
},
"mouser": {
"pn": "595-DP83826IRHBT",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "ModeSelect",
"type": "input",
"description": "Selects the operating mode: leave unconnected or pull up to VDDIO for ENHANCED mode, or short to GND for BASIC mode."
},
{
"number": "2",
"name": "CEXT",
"type": "passive",
"description": "External capacitor pin that must be connected through a 2 nF capacitor to GND."
},
{
"number": "3",
"name": "VDDA3V3",
"type": "power_in",
"description": "Analog supply input of 3.3 V (3.0 V to 3.6 V recommended range)."
},
{
"number": "4",
"name": "RD_M",
"type": "input",
"description": "Differential receive input (PMD) that is automatically configured for 10BASE-Te or 100BASE-TX signaling."
},
{
"number": "5",
"name": "RD_P",
"type": "input",
"description": "Differential receive input (PMD) that is automatically configured for 10BASE-Te or 100BASE-TX signaling."
},
{
"number": "6",
"name": "TD_M",
"type": "output",
"description": "Differential transmit output (PMD) configured for 10BASE-Te or 100BASE-TX signaling based on the PHY configuration."
},
{
"number": "7",
"name": "TD_P",
"type": "output",
"description": "Differential transmit output (PMD) configured for 10BASE-Te or 100BASE-TX signaling based on the PHY configuration."
},
{
"number": "8",
"name": "XO",
"type": "output",
"description": "Crystal output used only with a crystal; leave floating when a CMOS-level oscillator drives XI."
},
{
"number": "9",
"name": "XI/50MHzIn",
"type": "input",
"description": "Crystal or oscillator clock input: 25 MHz ±50 ppm in MII or RMII leader mode, and 50 MHz ±50 ppm CMOS oscillator in RMII follower mode."
},
{
"number": "10",
"name": "RBIAS",
"type": "passive",
"description": "Bias resistor pin requiring a 6.49 kΩ resistor with 1% precision connected to ground."
},
{
"number": "11",
"name": "MDIO",
"type": "bidirectional",
"description": "Management data I/O with an internal 10 kΩ pullup; an external pullup can be added if needed."
},
{
"number": "12",
"name": "MDC",
"type": "input",
"description": "Management data clock, with a maximum rate of 25 MHz and no minimum rate."
},
{
"number": "13",
"name": "Strap7/RX_D3",
"type": "output",
"description": "Receive data bit 3 in MII mode, or receive data bit 1 in RMII mode, synchronous to RX_CLK and valid when RX_DV is asserted."
},
{
"number": "14",
"name": "Strap8/RX_D2",
"type": "output",
"description": "Receive data bit 2 in MII mode, synchronous to RX_CLK and valid when RX_DV is asserted."
},
{
"number": "15",
"name": "Strap9/RX_D1",
"type": "output",
"description": "Receive data bit 1 in MII and RMII modes, synchronous to RX_CLK and valid when RX_DV is asserted."
},
{
"number": "16",
"name": "Strap0/RX_D0",
"type": "output",
"description": "Receive data bit 0 in MII and RMII modes, synchronous to RX_CLK and valid when RX_DV is asserted."
},
{
"number": "17",
"name": "VDDIO",
"type": "power_in",
"description": "I/O supply input of 3.3 V or 1.8 V."
},
{
"number": "18",
"name": "RX_DV/CRS_DV/Strap10",
"type": "output",
"description": "Receive data valid in MII mode, or combined carrier sense and receive data valid in RMII mode; can be configured as RX_DV in RMII repeater mode."
},
{
"number": "19",
"name": "RX_CLK/50MHz_RMII",
"type": "output",
"description": "Receive clock providing 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps in MII mode, or 50 MHz reference in RMII leader mode; unused input with pulldown in RMII follower mode."
},
{
"number": "20",
"name": "RX_ER/Strap6",
"type": "output",
"description": "Receive error output asserted for every reception error, including errors during Idle; this strap latches only at power-up."
},
{
"number": "21",
"name": "PWRDN/INT",
"type": "bidirectional",
"description": "Active-low power-down input by default, or open-drain interrupt output when configured by register; includes a weak 9.5 kΩ internal pullup."
},
{
"number": "22",
"name": "TX_CLK/Strap5",
"type": "output",
"description": "MII transmit clock providing 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps; unused in RMII mode."
},
{
"number": "23",
"name": "TX_EN",
"type": "input",
"description": "Transmit enable, presented on the rising edge of TX_CLK and active high, indicating valid TX_D data."
},
{
"number": "24",
"name": "TX_D0",
"type": "input",
"description": "Transmit data bit 0 from the MAC, synchronous to the rising edge of TX_CLK in MII mode or the reference clock in RMII mode."
},
{
"number": "25",
"name": "TX_D1",
"type": "input",
"description": "Transmit data bit 1 from the MAC, synchronous to the rising edge of TX_CLK in MII mode or the reference clock in RMII mode."
},
{
"number": "26",
"name": "TX_D2",
"type": "input",
"description": "Transmit data bit 2 from the MAC, used in MII mode and synchronous to TX_CLK."
},
{
"number": "27",
"name": "TX_D3",
"type": "input",
"description": "Transmit data bit 3 from the MAC, used in MII mode and synchronous to TX_CLK."
},
{
"number": "28",
"name": "COL/LED2/TX_ER/GPIO/Strap4",
"type": "output",
"description": "Collision detect in MII mode (always LOW in full duplex); defaults to LED2 in RMII mode and can be configured as TX_ER or GPIO by register."
},
{
"number": "29",
"name": "CRS/LED3/Strap3",
"type": "output",
"description": "Carrier sense in MII mode, asserted high when the medium is non-idle; defaults to LED3 in RMII mode."
},
{
"number": "30",
"name": "LED0/Strap2",
"type": "output",
"description": "LED indicating link status and transmit or receive activity; ON when link is good and blinks on activity, with polarity auto-detected."
},
{
"number": "31",
"name": "CLKOUT/LED1/Strap1",
"type": "output",
"description": "Provides a 25 MHz reference clock from XI by default after power-on reset, or acts as LED1 (ON at 100 Mbps link) when configured by strap or register."
},
{
"number": "32",
"name": "RST_N",
"type": "input",
"description": "Active-low reset input; asserting it low for at least 25 µs forces a reset and re-scans the strap pins."
},
{
"number": "33",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet defines two pin maps selected by ModeSelect (pin 1). This extraction uses the ENHANCED; The thermal pad on the RHB 32-pin QFN is described as 'connect to GND' but has no pin number in the ; The datasheet pin tables and package addendum confirm the RHB 32-pin VQFN (5.00 mm x 5.00 mm) for th",
"1/33 pins cited to the wrong page (name found elsewhere): ['8:XO@p5']"
],
"pages_sent": 32,
"cost_usd": 0.0539,
"at": "2026-11-06T02:14:08"
},
"datasheet": {
"url": "https://www.ti.com/lit/ds/symlink/dp83826i.pdf",
"pages": 114,
"sha256": "4e440fb8bd1cd44e",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 33,
"described": 33,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
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"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
5.0,
5.0,
0.875
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "5fa713ea46b36980895812ed853577889b7cb06d275041a39b99bc0be305dc79",
"checked": "2026-11-06",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "dp83826irhbt-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
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"footprint_binding": "identity",
"sha256": "37515eb16fc4a8e21297d7e4a69c1c3ccbc3847ac4f9745fcb280f7a747cba79",
"checked": "2026-11-06",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}