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DP83826IRHBT
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Texas Instruments Ethernet Controllers, VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DP83826IRHBT
Texas Instruments · Ethernet Controllers · VQFN-32(5x5)
DP83826IRHBT from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ModeSelect | input | Selects the operating mode: leave unconnected or pull up to VDDIO for ENHANCED mode, or short to GND for BASIC mode. |
| 2 | CEXT | passive | External capacitor pin that must be connected through a 2 nF capacitor to GND. |
| 3 | VDDA3V3 | power_in | Analog supply input of 3.3 V (3.0 V to 3.6 V recommended range). |
| 4 | RD_M | input | Differential receive input (PMD) that is automatically configured for 10BASE-Te or 100BASE-TX signaling. |
| 5 | RD_P | input | Differential receive input (PMD) that is automatically configured for 10BASE-Te or 100BASE-TX signaling. |
| 6 | TD_M | output | Differential transmit output (PMD) configured for 10BASE-Te or 100BASE-TX signaling based on the PHY configuration. |
| 7 | TD_P | output | Differential transmit output (PMD) configured for 10BASE-Te or 100BASE-TX signaling based on the PHY configuration. |
| 8 | XO | output | Crystal output used only with a crystal; leave floating when a CMOS-level oscillator drives XI. |
| 9 | XI/50MHzIn | input | Crystal or oscillator clock input: 25 MHz ±50 ppm in MII or RMII leader mode, and 50 MHz ±50 ppm CMOS oscillator in RMII follower mode. |
| 10 | RBIAS | passive | Bias resistor pin requiring a 6.49 kΩ resistor with 1% precision connected to ground. |
| 11 | MDIO | bidirectional | Management data I/O with an internal 10 kΩ pullup; an external pullup can be added if needed. |
| 12 | MDC | input | Management data clock, with a maximum rate of 25 MHz and no minimum rate. |
| 13 | Strap7/RX_D3 | output | Receive data bit 3 in MII mode, or receive data bit 1 in RMII mode, synchronous to RX_CLK and valid when RX_DV is asserted. |
| 14 | Strap8/RX_D2 | output | Receive data bit 2 in MII mode, synchronous to RX_CLK and valid when RX_DV is asserted. |
| 15 | Strap9/RX_D1 | output | Receive data bit 1 in MII and RMII modes, synchronous to RX_CLK and valid when RX_DV is asserted. |
| 16 | Strap0/RX_D0 | output | Receive data bit 0 in MII and RMII modes, synchronous to RX_CLK and valid when RX_DV is asserted. |
| 17 | VDDIO | power_in | I/O supply input of 3.3 V or 1.8 V. |
| 18 | RX_DV/CRS_DV/Strap10 | output | Receive data valid in MII mode, or combined carrier sense and receive data valid in RMII mode; can be configured as RX_DV in RMII repeater mode. |
| 19 | RX_CLK/50MHz_RMII | output | Receive clock providing 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps in MII mode, or 50 MHz reference in RMII leader mode; unused input with pulldown in RMII follower mode. |
| 20 | RX_ER/Strap6 | output | Receive error output asserted for every reception error, including errors during Idle; this strap latches only at power-up. |
| 21 | PWRDN/INT | bidirectional | Active-low power-down input by default, or open-drain interrupt output when configured by register; includes a weak 9.5 kΩ internal pullup. |
| 22 | TX_CLK/Strap5 | output | MII transmit clock providing 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps; unused in RMII mode. |
| 23 | TX_EN | input | Transmit enable, presented on the rising edge of TX_CLK and active high, indicating valid TX_D data. |
| 24 | TX_D0 | input | Transmit data bit 0 from the MAC, synchronous to the rising edge of TX_CLK in MII mode or the reference clock in RMII mode. |
| 25 | TX_D1 | input | Transmit data bit 1 from the MAC, synchronous to the rising edge of TX_CLK in MII mode or the reference clock in RMII mode. |
| 26 | TX_D2 | input | Transmit data bit 2 from the MAC, used in MII mode and synchronous to TX_CLK. |
| 27 | TX_D3 | input | Transmit data bit 3 from the MAC, used in MII mode and synchronous to TX_CLK. |
| 28 | COL/LED2/TX_ER/GPIO/Strap4 | output | Collision detect in MII mode (always LOW in full duplex); defaults to LED2 in RMII mode and can be configured as TX_ER or GPIO by register. |
| 29 | CRS/LED3/Strap3 | output | Carrier sense in MII mode, asserted high when the medium is non-idle; defaults to LED3 in RMII mode. |
| 30 | LED0/Strap2 | output | LED indicating link status and transmit or receive activity; ON when link is good and blinks on activity, with polarity auto-detected. |
| 31 | CLKOUT/LED1/Strap1 | output | Provides a 25 MHz reference clock from XI by default after power-on reset, or acts as LED1 (ON at 100 Mbps link) when configured by strap or register. |
| 32 | RST_N | input | Active-low reset input; asserting it low for at least 25 µs forces a reset and re-scans the strap pins. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32(5x5) |
| Category | Interface |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog supply voltage | VDDA3V3 | -0.3 | 4 | V | 10 | ||
| IO supply voltage VDDIO3V3 | VDDIO3V3 | -0.3 | 4 | V | 10 | ||
| IO supply voltage VDDIO1V8 | VDDIO1V8 | -0.3 | 2.1 | V | 10 | ||
| Storage Temperature | Tstg | -65 | 150 | °C | 10 | ||
| MDI pins TX_P, TX_M, RX_P, RX_M | -0.6 | 4 | V | 10 | |||
| MAC interface pins TX_CLK, TX_D[3:0], TX_EN, TX_ER, RX_CLK, RX_D[3:0], RX_ER, RX_DV, CRS, COL | -0.3 | 4 | V | 10 | |||
| Serial management interface pins MDIO, MDC | -0.3 | 4 | V | 10 | |||
| Crystal/Oscillator pins XI, XO | -0.3 | 4 | V | 10 | |||
| Reset pin RST_N | RST_N | -0.3 | 4 | V | 10 | ||
| Analog supply voltage | VDDA3V3 | 3 | 3.3 | 3.6 | V | 10 | |
| IO supply voltage VDDIO3V3 | VDDIO3V3 | 3 | 3.3 | 3.6 | V | 10 | |
| IO supply voltage VDDIO1V8 | VDDIO1V8 | 1.62 | 1.8 | 1.98 | V | 10 | |
| Operating Free Air Temperature (DP83826I) | TA | -40 | 25 | 85 | °C | 10 | |
| VOD Differential output voltage (100BaseTx) | VOD | 950 | 1050 | mV | 12 | ||
| VOD Output differential voltage (10BaseTe) | VOD | 1.54 | 1.75 | 1.96 | V | 12 | |
| Power consumption baseline I(VDDA3V3=3V3) MII (100BaseTx) | I(VDDA3V3=3V3) | 45 | 53 | mA | Active mode, 50% Traffic, Packet Size 1518, Random Content, 150 meter Cable | 12 | |
| Power consumption worst case I(VDDA3V3=3V3) MII (100BaseTx) | I(VDDA3V3=3V3) | 44 | 55 | mA | Active mode worst case, 100% Traffic, Packet Size 1518, Random Content, 150 meter Cable | 12 | |
| Power consumption baseline I(VDDIO=3V3) MII (100BaseTx) | I(VDDIO=3V3) | 8 | 14 | mA | Active mode, 50% Traffic, Packet Size 1518, Random Content, 150 meter Cable | 12 | |
| Power consumption baseline I(VDDIO=1V8) MII (100BaseTx) | I(VDDIO=1V8) | 5 | 7 | mA | Active mode, 50% Traffic, Packet Size 1518, Random Content, 150 meter Cable | 12 | |
| Power Down current I(AVDD3V3=3V3) | I(AVDD3V3=3V3) | 11 | mA | IEEE Power Down | 13 | ||
| Power consumption RESET I(AVDD3V3=3V3) | I(AVDD3V3=3V3) | 12.5 | mA | RESET | 13 | ||
| High Level bootstrap threshold 3V3 | VIH_3v3 | 1.3 | V | 13 | |||
| Low Level bootstrap threshold 3V3 | VIL_3v3 | 0.6 | V | 13 | |||
| High Level bootstrap threshold 1V8 | VIH_1v8 | 1.3 | V | 13 | |||
| Low Level bootstrap threshold 1V8 | VIL_1v8 | 0.6 | V | 13 | |||
| External load capacitance (crystal oscillator) | COSC_EXT | 15 | 30 | pF | 13 | ||
| High level input voltage (3.3V) | VIH_3V3 | 1.7 | V | VDDIO = 3.3V ±10% | 14 | ||
| Low level input voltage (3.3V) | VIL_3V3 | 0.8 | V | VDDIO = 3.3V ±10% | 14 | ||
| High level output voltage (3.3V) | VOH_3V3 | 2.4 | V | IOH = -2mA, VDDIO = 3.3V ±10% | 14 | ||
| Low level output voltage (3.3V) | VOL_3V3 | 0.4 | V | IOL = 2mA, VDDIO = 3.3V ±10% | 14 | ||
| High level input voltage (1.8V) | VIH_1V8 | 0.65 | x VDDIO | VDDIO = 1.8V ±10% | 14 | ||
| Low level input voltage (1.8V) | VIL_1V8 | 0.35 | x VDDIO | VDDIO = 1.8V ±10% | 14 | ||
| Low level output voltage (1.8V) | VOL_1V8 | 0.45 | V | IOL = 2mA, VDDIO = 1.8V ±10% | 14 | ||
| Input high current (85 °C) | IIH | 15 | µA | TA = -40℃ to 85℃, VIN=VDDIO | 14 | ||
| Input low current (85 °C) | IIL | 15 | µA | TA = -40℃ to 85℃, VIN=GND | 14 | ||
| Tri-state output high current (85 °C) | IOZH | -15 | 15 | µA | TA = -40℃ to 85℃ | 14 | |
| Tri-state output low current (85 °C) | IOZL | -15 | 15 | µA | TA = -40℃ to 85℃ | 14 | |
| Internal pull down resistor | RPD | 7.5 | 10 | 12.5 | kΩ | 14 | |
| Internal pull up resistor | RPU | 7.5 | 10 | 12.5 | kΩ | 14 | |
| 100M MII Receive RX_CLK high / low time | T1 | 16 | 20 | 24 | ns | 15 | |
| Reset pulse width | T1 | 25 | µs | Minimum reset pulse width to be able to reset (w/o debouncing caps) | 15 | ||
| Thermal resistance junction-to-ambient | RθJA | 52 | °C/W | 11 | |||
| Thermal resistance junction-to-case (top) | RθJC(top) | 42 | °C/W | 11 | |||
| Thermal resistance junction-to-case (bottom) | RθJC(bot) | 11.9 | °C/W | 11 | |||
| Thermal resistance junction-to-board | RθJB | 31.5 | °C/W | 11 | |||
| RBIAS bias resistor tolerance | RBIAS | -1 | 1 | % | 1% precision connected to ground | 5 | |
| RBIAS bias resistor value | RBIAS | 6.49 | kΩ | connected to ground | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-Te standard. Each link pulse is nominally 100ns in duration and transmitted every 16ms in the absence of transmit data. Lin | 40 |
CAD (KiCad official)
- Symbol:
DP83826IRHBT - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
dp83826irhbt-etched.step/dp83826irhbt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dp83826irhbt.step/dp83826irhbt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (114 pp, sha256
4e440fb8bd1cd44e, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DP83826IRHBT
**Texas Instruments** · Ethernet Controllers · VQFN-32(5x5)
DP83826IRHBT from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ModeSelect | input | Selects the operating mode: leave unconnected or pull up to VDDIO for ENHANCED mode, or short to GND for BASIC mode. |
| 2 | CEXT | passive | External capacitor pin that must be connected through a 2 nF capacitor to GND. |
| 3 | VDDA3V3 | power_in | Analog supply input of 3.3 V (3.0 V to 3.6 V recommended range). |
| 4 | RD_M | input | Differential receive input (PMD) that is automatically configured for 10BASE-Te or 100BASE-TX signaling. |
| 5 | RD_P | input | Differential receive input (PMD) that is automatically configured for 10BASE-Te or 100BASE-TX signaling. |
| 6 | TD_M | output | Differential transmit output (PMD) configured for 10BASE-Te or 100BASE-TX signaling based on the PHY configuration. |
| 7 | TD_P | output | Differential transmit output (PMD) configured for 10BASE-Te or 100BASE-TX signaling based on the PHY configuration. |
| 8 | XO | output | Crystal output used only with a crystal; leave floating when a CMOS-level oscillator drives XI. |
| 9 | XI/50MHzIn | input | Crystal or oscillator clock input: 25 MHz ±50 ppm in MII or RMII leader mode, and 50 MHz ±50 ppm CMOS oscillator in RMII follower mode. |
| 10 | RBIAS | passive | Bias resistor pin requiring a 6.49 kΩ resistor with 1% precision connected to ground. |
| 11 | MDIO | bidirectional | Management data I/O with an internal 10 kΩ pullup; an external pullup can be added if needed. |
| 12 | MDC | input | Management data clock, with a maximum rate of 25 MHz and no minimum rate. |
| 13 | Strap7/RX_D3 | output | Receive data bit 3 in MII mode, or receive data bit 1 in RMII mode, synchronous to RX_CLK and valid when RX_DV is asserted. |
| 14 | Strap8/RX_D2 | output | Receive data bit 2 in MII mode, synchronous to RX_CLK and valid when RX_DV is asserted. |
| 15 | Strap9/RX_D1 | output | Receive data bit 1 in MII and RMII modes, synchronous to RX_CLK and valid when RX_DV is asserted. |
| 16 | Strap0/RX_D0 | output | Receive data bit 0 in MII and RMII modes, synchronous to RX_CLK and valid when RX_DV is asserted. |
| 17 | VDDIO | power_in | I/O supply input of 3.3 V or 1.8 V. |
| 18 | RX_DV/CRS_DV/Strap10 | output | Receive data valid in MII mode, or combined carrier sense and receive data valid in RMII mode; can be configured as RX_DV in RMII repeater mode. |
| 19 | RX_CLK/50MHz_RMII | output | Receive clock providing 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps in MII mode, or 50 MHz reference in RMII leader mode; unused input with pulldown in RMII follower mode. |
| 20 | RX_ER/Strap6 | output | Receive error output asserted for every reception error, including errors during Idle; this strap latches only at power-up. |
| 21 | PWRDN/INT | bidirectional | Active-low power-down input by default, or open-drain interrupt output when configured by register; includes a weak 9.5 kΩ internal pullup. |
| 22 | TX_CLK/Strap5 | output | MII transmit clock providing 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps; unused in RMII mode. |
| 23 | TX_EN | input | Transmit enable, presented on the rising edge of TX_CLK and active high, indicating valid TX_D data. |
| 24 | TX_D0 | input | Transmit data bit 0 from the MAC, synchronous to the rising edge of TX_CLK in MII mode or the reference clock in RMII mode. |
| 25 | TX_D1 | input | Transmit data bit 1 from the MAC, synchronous to the rising edge of TX_CLK in MII mode or the reference clock in RMII mode. |
| 26 | TX_D2 | input | Transmit data bit 2 from the MAC, used in MII mode and synchronous to TX_CLK. |
| 27 | TX_D3 | input | Transmit data bit 3 from the MAC, used in MII mode and synchronous to TX_CLK. |
| 28 | COL/LED2/TX_ER/GPIO/Strap4 | output | Collision detect in MII mode (always LOW in full duplex); defaults to LED2 in RMII mode and can be configured as TX_ER or GPIO by register. |
| 29 | CRS/LED3/Strap3 | output | Carrier sense in MII mode, asserted high when the medium is non-idle; defaults to LED3 in RMII mode. |
| 30 | LED0/Strap2 | output | LED indicating link status and transmit or receive activity; ON when link is good and blinks on activity, with polarity auto-detected. |
| 31 | CLKOUT/LED1/Strap1 | output | Provides a 25 MHz reference clock from XI by default after power-on reset, or acts as LED1 (ON at 100 Mbps link) when configured by strap or register. |
| 32 | RST_N | input | Active-low reset input; asserting it low for at least 25 µs forces a reset and re-scans the strap pins. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32(5x5) |
| Category | Interface |
| Pins | 33 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog supply voltage | VDDA3V3 | -0.3 | | 4 | V | | 10 |
| IO supply voltage VDDIO3V3 | VDDIO3V3 | -0.3 | | 4 | V | | 10 |
| IO supply voltage VDDIO1V8 | VDDIO1V8 | -0.3 | | 2.1 | V | | 10 |
| Storage Temperature | Tstg | -65 | | 150 | °C | | 10 |
| MDI pins TX_P, TX_M, RX_P, RX_M | | -0.6 | | 4 | V | | 10 |
| MAC interface pins TX_CLK, TX_D[3:0], TX_EN, TX_ER, RX_CLK, RX_D[3:0], RX_ER, RX_DV, CRS, COL | | -0.3 | | 4 | V | | 10 |
| Serial management interface pins MDIO, MDC | | -0.3 | | 4 | V | | 10 |
| Crystal/Oscillator pins XI, XO | | -0.3 | | 4 | V | | 10 |
| Reset pin RST_N | RST_N | -0.3 | | 4 | V | | 10 |
| Analog supply voltage | VDDA3V3 | 3 | 3.3 | 3.6 | V | | 10 |
| IO supply voltage VDDIO3V3 | VDDIO3V3 | 3 | 3.3 | 3.6 | V | | 10 |
| IO supply voltage VDDIO1V8 | VDDIO1V8 | 1.62 | 1.8 | 1.98 | V | | 10 |
| Operating Free Air Temperature (DP83826I) | TA | -40 | 25 | 85 | °C | | 10 |
| VOD Differential output voltage (100BaseTx) | VOD | 950 | | 1050 | mV | | 12 |
| VOD Output differential voltage (10BaseTe) | VOD | 1.54 | 1.75 | 1.96 | V | | 12 |
| Power consumption baseline I(VDDA3V3=3V3) MII (100BaseTx) | I(VDDA3V3=3V3) | 45 | | 53 | mA | Active mode, 50% Traffic, Packet Size 1518, Random Content, 150 meter Cable | 12 |
| Power consumption worst case I(VDDA3V3=3V3) MII (100BaseTx) | I(VDDA3V3=3V3) | 44 | | 55 | mA | Active mode worst case, 100% Traffic, Packet Size 1518, Random Content, 150 meter Cable | 12 |
| Power consumption baseline I(VDDIO=3V3) MII (100BaseTx) | I(VDDIO=3V3) | 8 | | 14 | mA | Active mode, 50% Traffic, Packet Size 1518, Random Content, 150 meter Cable | 12 |
| Power consumption baseline I(VDDIO=1V8) MII (100BaseTx) | I(VDDIO=1V8) | 5 | | 7 | mA | Active mode, 50% Traffic, Packet Size 1518, Random Content, 150 meter Cable | 12 |
| Power Down current I(AVDD3V3=3V3) | I(AVDD3V3=3V3) | | | 11 | mA | IEEE Power Down | 13 |
| Power consumption RESET I(AVDD3V3=3V3) | I(AVDD3V3=3V3) | | | 12.5 | mA | RESET | 13 |
| High Level bootstrap threshold 3V3 | VIH_3v3 | 1.3 | | | V | | 13 |
| Low Level bootstrap threshold 3V3 | VIL_3v3 | | | 0.6 | V | | 13 |
| High Level bootstrap threshold 1V8 | VIH_1v8 | 1.3 | | | V | | 13 |
| Low Level bootstrap threshold 1V8 | VIL_1v8 | | | 0.6 | V | | 13 |
| External load capacitance (crystal oscillator) | COSC_EXT | 15 | | 30 | pF | | 13 |
| High level input voltage (3.3V) | VIH_3V3 | 1.7 | | | V | VDDIO = 3.3V ±10% | 14 |
| Low level input voltage (3.3V) | VIL_3V3 | | | 0.8 | V | VDDIO = 3.3V ±10% | 14 |
| High level output voltage (3.3V) | VOH_3V3 | 2.4 | | | V | IOH = -2mA, VDDIO = 3.3V ±10% | 14 |
| Low level output voltage (3.3V) | VOL_3V3 | | | 0.4 | V | IOL = 2mA, VDDIO = 3.3V ±10% | 14 |
| High level input voltage (1.8V) | VIH_1V8 | 0.65 | | | x VDDIO | VDDIO = 1.8V ±10% | 14 |
| Low level input voltage (1.8V) | VIL_1V8 | | | 0.35 | x VDDIO | VDDIO = 1.8V ±10% | 14 |
| Low level output voltage (1.8V) | VOL_1V8 | | | 0.45 | V | IOL = 2mA, VDDIO = 1.8V ±10% | 14 |
| Input high current (85 °C) | IIH | | | 15 | µA | TA = -40℃ to 85℃, VIN=VDDIO | 14 |
| Input low current (85 °C) | IIL | | | 15 | µA | TA = -40℃ to 85℃, VIN=GND | 14 |
| Tri-state output high current (85 °C) | IOZH | -15 | | 15 | µA | TA = -40℃ to 85℃ | 14 |
| Tri-state output low current (85 °C) | IOZL | -15 | | 15 | µA | TA = -40℃ to 85℃ | 14 |
| Internal pull down resistor | RPD | 7.5 | 10 | 12.5 | kΩ | | 14 |
| Internal pull up resistor | RPU | 7.5 | 10 | 12.5 | kΩ | | 14 |
| 100M MII Receive RX_CLK high / low time | T1 | 16 | 20 | 24 | ns | | 15 |
| Reset pulse width | T1 | 25 | | | µs | Minimum reset pulse width to be able to reset (w/o debouncing caps) | 15 |
| Thermal resistance junction-to-ambient | RθJA | | 52 | | °C/W | | 11 |
| Thermal resistance junction-to-case (top) | RθJC(top) | | 42 | | °C/W | | 11 |
| Thermal resistance junction-to-case (bottom) | RθJC(bot) | | 11.9 | | °C/W | | 11 |
| Thermal resistance junction-to-board | RθJB | | 31.5 | | °C/W | | 11 |
| RBIAS bias resistor tolerance | RBIAS | -1 | | 1 | % | 1% precision connected to ground | 5 |
| RBIAS bias resistor value | RBIAS | | 6.49 | | kΩ | connected to ground | 5 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | | The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-Te standard. Each link pulse is nominally 100ns in duration and transmitted every 16ms in the absence of transmit data. Lin | 40 |
## CAD (KiCad official)
- Symbol: `DP83826IRHBT`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files: `dp83826irhbt-etched.step` / `dp83826irhbt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83826irhbt.step` / `dp83826irhbt.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dp83826i.pdf) (114 pp, sha256 `4e440fb8bd1cd44e`, retrieved 2026-11-06, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dp83826irhbt-datasheet.pdf)