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DP83826ERHBT
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Texas Instruments Ethernet Transceivers, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# DP83826ERHBT++**Texas Instruments** · Ethernet Transceivers · VQFN-32-EP(5x5)++DP83826ERHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | ModeSelect | input | Mode selection input with internal pull-up; leave NC or pull to VDDIO for Enhanced Mode, short to GND for Basic Mode. |+| 2 | CEXT | passive | External capacitor node for clock stabilization; connect via 2nF capacitor to GND. |+| 3 | VDDA3V3 | power_in | Analog power supply input; 3.3V with appropriate decoupling capacitors per power section. |+| 4 | RD_M | input | Differential receive input minus; auto-configured for 10BASE-Te or 100BASE-TX according to IEEE 802.3. |+| 5 | RD_P | input | Differential receive input plus; auto-configured for 10BASE-Te or 100BASE-TX according to IEEE 802.3. |+| 6 | TD_M | output | Differential transmit output minus; configured as 10BASE-Te or 100BASE-TX per strap configuration. |+| 7 | TD_P | output | Differential transmit output plus; configured as 10BASE-Te or 100BASE-TX per strap configuration. |+| 8 | XO | output | Crystal oscillator output; leave floating when using CMOS-level oscillator on XI pin. |+| 9 | XI/50MHzIn | input | Crystal or oscillator input; accepts 25MHz ±50ppm crystal (MII/RMII leader) or 50MHz ±50ppm CMOS oscillator (RMII follower). |+| 10 | RBIAS | passive | Bias resistor node; connect 6.49kΩ ±1% resistor to ground. |+| 11 | MDIO | bidirectional | Bidirectional management data I/O for SMI protocol; has 10kΩ internal pull-up requiring external pull-up resistor. |+| 12 | MDC | input | Management data clock input; synchronizes MDIO transactions at maximum 25MHz with no minimum frequency. |+| 13 | RX_D3 | output | Receive data output bit 3; valid when RX_DV asserted, synchronized with RX_CLK rising edge. |+| 14 | RX_D2 | output | Receive data output bit 2; valid when RX_DV asserted, synchronized with RX_CLK rising edge. |+| 15 | RX_D1 | output | Receive data output bit 1; valid when RX_DV asserted, synchronized with RX_CLK rising edge. |+| 16 | RX_D0 | output | Receive data output bit 0; valid when RX_DV asserted, synchronized with RX_CLK rising edge. |+| 17 | VDDIO | power_in | I/O power supply; accepts 3.3V ±0.3V or 1.8V ±0.18V with appropriate decoupling capacitors. |+| 18 | RX_DV/CRS_DV | output | Receive data valid output in MII mode or combined carrier sense in RMII mode; active high indicating valid data on RX_D. |+| 19 | RX_CLK/50MHz_RMII | output | Receive clock output; provides 25MHz (100Mbps) or 2.5MHz (10Mbps) in MII mode; 50MHz in RMII leader mode. |+| 20 | RX_ER | output | Receive error output; indicates detection of error symbols in received packets, synchronized with RX_CLK rising edge. |+| 21 | PWRDN/INT | bidirectional | Power down input or interrupt output; defaults to power down function with low active signal, configurable to interrupt via register. |+| 22 | TX_CLK | output | Transmit clock output; provides 25MHz (100Mbps) or 2.5MHz (10Mbps) in MII mode with constant phase relative to XI. |+| 23 | TX_EN | input | Transmit enable input; synchronized with TX_CLK rising edge, indicates valid data on TX_D[3:0] (MII) or TX_D[1:0] (RMII). |+| 24 | TX_D0 | input | Transmit data input bit 0; synchronized with TX_CLK rising edge in MII or reference clock rising edge in RMII. |+| 25 | TX_D1 | input | Transmit data input bit 1; synchronized with TX_CLK rising edge in MII or reference clock rising edge in RMII. |+| 26 | TX_D2 | input | Transmit data input bit 2; synchronized with TX_CLK rising edge in MII or reference clock rising edge in RMII. |+| 27 | TX_D3 | input | Transmit data input bit 3; synchronized with TX_CLK rising edge in MII or reference clock rising edge in RMII. |+| 28 | COL/LED2/TX_ER/GPIO | output | Collision detection output in MII (low in full-duplex, high when both TX and RX active in half-duplex); configurable as LED2/TX_ER/GPIO via register. |+| 29 | CRS/LED3 | output | Carrier sense output in MII (high when medium active); configurable as LED3 via register. |+| 30 | LED0 | output | Link status LED output; indicates link status with optional transmit/receive activity blink per register and strap configuration. |+| 31 | CLKOUT/LED1 | output | Clock output (Enhanced Mode default); outputs 25MHz reference from XI at power-up, configurable as LED1 via strap, disabled only in deep power down. |+| 32 | RST_N | input | Active-low reset input with internal pull-up; minimum 25µs pulse triggers device reset and strap re-scan with internal register reset. |+| 33 | GND | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-32-EP(5x5) |+| Category | Interface |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `DP83826ERHBT`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `dp83826erhbt-etched.step` / `dp83826erhbt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83826erhbt.step` / `dp83826erhbt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/dp83826e) (115 pp, sha256 `0ddec6391c36bec1`, retrieved 2026-10-01, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/dp83826erhbt-datasheet.pdf)
page.jsonadded+309@@ -0,0 +1,309 @@+{+ "slug": "dp83826erhbt",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Ethernet Transceivers, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "dp83826erhbt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "dp83826erhbt.kicad_sym",+ "dp83826erhbt.kicad_mod",+ "dp83826erhbt.glb",+ "dp83826erhbt.step",+ "dp83826erhbt.lbr",+ "docs/hero.png",+ "docs/dp83826erhbt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DP83826ERHBT",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-32-EP(5x5)",+ "pin_count": 33,+ "category": "Interface",+ "subcategory": "Ethernet Transceivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/dp83826e",+ "parts": {+ "symbol": "dp83826erhbt.kicad_sym",+ "footprint": "dp83826erhbt.kicad_mod",+ "model_3d": "dp83826erhbt-etched.glb",+ "model_3d_plain": "dp83826erhbt.glb",+ "model_3d_step": "dp83826erhbt-etched.step",+ "model_3d_step_plain": "dp83826erhbt.step",+ "lbr": "dp83826erhbt.lbr"+ },+ "distributor_links": {+ "lcsc": "C1855771",+ "digikey": "296-DP83826ERHBTTR-ND",+ "mouser": "595-DP83826ERHBT"+ },+ "distributor_check": {+ "checked_at": "2026-10-01T06:33:06Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-DP83826ERHBTTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DP83826ERHBT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "ModeSelect",+ "type": "input",+ "description": "Mode selection input with internal pull-up; leave NC or pull to VDDIO for Enhanced Mode, short to GND for Basic Mode."+ },+ {+ "number": "2",+ "name": "CEXT",+ "type": "passive",+ "description": "External capacitor node for clock stabilization; connect via 2nF capacitor to GND."+ },+ {+ "number": "3",+ "name": "VDDA3V3",+ "type": "power_in",+ "description": "Analog power supply input; 3.3V with appropriate decoupling capacitors per power section."+ },+ {+ "number": "4",+ "name": "RD_M",+ "type": "input",+ "description": "Differential receive input minus; auto-configured for 10BASE-Te or 100BASE-TX according to IEEE 802.3."+ },+ {+ "number": "5",+ "name": "RD_P",+ "type": "input",+ "description": "Differential receive input plus; auto-configured for 10BASE-Te or 100BASE-TX according to IEEE 802.3."+ },+ {+ "number": "6",+ "name": "TD_M",+ "type": "output",+ "description": "Differential transmit output minus; configured as 10BASE-Te or 100BASE-TX per strap configuration."+ },+ {+ "number": "7",+ "name": "TD_P",+ "type": "output",+ "description": "Differential transmit output plus; configured as 10BASE-Te or 100BASE-TX per strap configuration."+ },+ {+ "number": "8",+ "name": "XO",+ "type": "output",+ "description": "Crystal oscillator output; leave floating when using CMOS-level oscillator on XI pin."+ },+ {+ "number": "9",+ "name": "XI/50MHzIn",+ "type": "input",+ "description": "Crystal or oscillator input; accepts 25MHz ±50ppm crystal (MII/RMII leader) or 50MHz ±50ppm CMOS oscillator (RMII follower)."+ },+ {+ "number": "10",+ "name": "RBIAS",+ "type": "passive",+ "description": "Bias resistor node; connect 6.49kΩ ±1% resistor to ground."+ },+ {+ "number": "11",+ "name": "MDIO",+ "type": "bidirectional",+ "description": "Bidirectional management data I/O for SMI protocol; has 10kΩ internal pull-up requiring external pull-up resistor."+ },+ {+ "number": "12",+ "name": "MDC",+ "type": "input",+ "description": "Management data clock input; synchronizes MDIO transactions at maximum 25MHz with no minimum frequency."+ },+ {+ "number": "13",+ "name": "RX_D3",+ "type": "output",+ "description": "Receive data output bit 3; valid when RX_DV asserted, synchronized with RX_CLK rising edge."+ },+ {+ "number": "14",+ "name": "RX_D2",+ "type": "output",+ "description": "Receive data output bit 2; valid when RX_DV asserted, synchronized with RX_CLK rising edge."+ },+ {+ "number": "15",+ "name": "RX_D1",+ "type": "output",+ "description": "Receive data output bit 1; valid when RX_DV asserted, synchronized with RX_CLK rising edge."+ },+ {+ "number": "16",+ "name": "RX_D0",+ "type": "output",+ "description": "Receive data output bit 0; valid when RX_DV asserted, synchronized with RX_CLK rising edge."+ },+ {+ "number": "17",+ "name": "VDDIO",+ "type": "power_in",+ "description": "I/O power supply; accepts 3.3V ±0.3V or 1.8V ±0.18V with appropriate decoupling capacitors."+ },+ {+ "number": "18",+ "name": "RX_DV/CRS_DV",+ "type": "output",+ "description": "Receive data valid output in MII mode or combined carrier sense in RMII mode; active high indicating valid data on RX_D."+ },+ {+ "number": "19",+ "name": "RX_CLK/50MHz_RMII",+ "type": "output",+ "description": "Receive clock output; provides 25MHz (100Mbps) or 2.5MHz (10Mbps) in MII mode; 50MHz in RMII leader mode."+ },+ {+ "number": "20",+ "name": "RX_ER",+ "type": "output",+ "description": "Receive error output; indicates detection of error symbols in received packets, synchronized with RX_CLK rising edge."+ },+ {+ "number": "21",+ "name": "PWRDN/INT",+ "type": "bidirectional",+ "description": "Power down input or interrupt output; defaults to power down function with low active signal, configurable to interrupt via register."+ },+ {+ "number": "22",+ "name": "TX_CLK",+ "type": "output",+ "description": "Transmit clock output; provides 25MHz (100Mbps) or 2.5MHz (10Mbps) in MII mode with constant phase relative to XI."+ },+ {+ "number": "23",+ "name": "TX_EN",+ "type": "input",+ "description": "Transmit enable input; synchronized with TX_CLK rising edge, indicates valid data on TX_D[3:0] (MII) or TX_D[1:0] (RMII)."+ },+ {+ "number": "24",+ "name": "TX_D0",+ "type": "input",+ "description": "Transmit data input bit 0; synchronized with TX_CLK rising edge in MII or reference clock rising edge in RMII."+ },+ {+ "number": "25",+ "name": "TX_D1",+ "type": "input",+ "description": "Transmit data input bit 1; synchronized with TX_CLK rising edge in MII or reference clock rising edge in RMII."+ },+ {+ "number": "26",+ "name": "TX_D2",+ "type": "input",+ "description": "Transmit data input bit 2; synchronized with TX_CLK rising edge in MII or reference clock rising edge in RMII."+ },+ {+ "number": "27",+ "name": "TX_D3",+ "type": "input",+ "description": "Transmit data input bit 3; synchronized with TX_CLK rising edge in MII or reference clock rising edge in RMII."+ },+ {+ "number": "28",+ "name": "COL/LED2/TX_ER/GPIO",+ "type": "output",+ "description": "Collision detection output in MII (low in full-duplex, high when both TX and RX active in half-duplex); configurable as LED2/TX_ER/GPIO via register."+ },+ {+ "number": "29",+ "name": "CRS/LED3",+ "type": "output",+ "description": "Carrier sense output in MII (high when medium active); configurable as LED3 via register."+ },+ {+ "number": "30",+ "name": "LED0",+ "type": "output",+ "description": "Link status LED output; indicates link status with optional transmit/receive activity blink per register and strap configuration."+ },+ {+ "number": "31",+ "name": "CLKOUT/LED1",+ "type": "output",+ "description": "Clock output (Enhanced Mode default); outputs 25MHz reference from XI at power-up, configurable as LED1 via strap, disabled only in deep power down."+ },+ {+ "number": "32",+ "name": "RST_N",+ "type": "input",+ "description": "Active-low reset input with internal pull-up; minimum 25µs pulse triggers device reset and strap re-scan with internal register reset."+ },+ {+ "number": "33",+ "name": "GND",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Thermal pad (exposed pad on bottom of package) must connect to GND but is not numbered in standard p; Enhanced Mode vs Basic Mode function differences: Pin 21 is PWRDN/INT in Enhanced Mode but INT only ; External passive components required per datasheet: 2nF capacitor must connect CEXT pin to GND; 6.49",+ "exposed pad 33 added from the footprint"+ ],+ "pages_sent": 73,+ "cost_usd": 0.528,+ "at": "2026-10-01T06:32:49"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/dp83826e",+ "pages": 115,+ "sha256": "0ddec6391c36bec1",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}