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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83826ERHBT

Texas Instruments · Ethernet Transceivers · VQFN-32-EP(5x5)

DP83826ERHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ModeSelect	input	Mode selection input with internal pull-up; leave NC or pull to VDDIO for Enhanced Mode, short to GND for Basic Mode.
2	CEXT	passive	External capacitor node for clock stabilization; connect via 2nF capacitor to GND.
3	VDDA3V3	power_in	Analog power supply input; 3.3V with appropriate decoupling capacitors per power section.
4	RD_M	input	Differential receive input minus; auto-configured for 10BASE-Te or 100BASE-TX according to IEEE 802.3.
5	RD_P	input	Differential receive input plus; auto-configured for 10BASE-Te or 100BASE-TX according to IEEE 802.3.
6	TD_M	output	Differential transmit output minus; configured as 10BASE-Te or 100BASE-TX per strap configuration.
7	TD_P	output	Differential transmit output plus; configured as 10BASE-Te or 100BASE-TX per strap configuration.
8	XO	output	Crystal oscillator output; leave floating when using CMOS-level oscillator on XI pin.
9	XI/50MHzIn	input	Crystal or oscillator input; accepts 25MHz ±50ppm crystal (MII/RMII leader) or 50MHz ±50ppm CMOS oscillator (RMII follower).
10	RBIAS	passive	Bias resistor node; connect 6.49kΩ ±1% resistor to ground.
11	MDIO	bidirectional	Bidirectional management data I/O for SMI protocol; has 10kΩ internal pull-up requiring external pull-up resistor.
12	MDC	input	Management data clock input; synchronizes MDIO transactions at maximum 25MHz with no minimum frequency.
13	RX_D3	output	Receive data output bit 3; valid when RX_DV asserted, synchronized with RX_CLK rising edge.
14	RX_D2	output	Receive data output bit 2; valid when RX_DV asserted, synchronized with RX_CLK rising edge.
15	RX_D1	output	Receive data output bit 1; valid when RX_DV asserted, synchronized with RX_CLK rising edge.
16	RX_D0	output	Receive data output bit 0; valid when RX_DV asserted, synchronized with RX_CLK rising edge.
17	VDDIO	power_in	I/O power supply; accepts 3.3V ±0.3V or 1.8V ±0.18V with appropriate decoupling capacitors.
18	RX_DV/CRS_DV	output	Receive data valid output in MII mode or combined carrier sense in RMII mode; active high indicating valid data on RX_D.
19	RX_CLK/50MHz_RMII	output	Receive clock output; provides 25MHz (100Mbps) or 2.5MHz (10Mbps) in MII mode; 50MHz in RMII leader mode.
20	RX_ER	output	Receive error output; indicates detection of error symbols in received packets, synchronized with RX_CLK rising edge.
21	PWRDN/INT	bidirectional	Power down input or interrupt output; defaults to power down function with low active signal, configurable to interrupt via register.
22	TX_CLK	output	Transmit clock output; provides 25MHz (100Mbps) or 2.5MHz (10Mbps) in MII mode with constant phase relative to XI.
23	TX_EN	input	Transmit enable input; synchronized with TX_CLK rising edge, indicates valid data on TX_D[3:0] (MII) or TX_D[1:0] (RMII).
24	TX_D0	input	Transmit data input bit 0; synchronized with TX_CLK rising edge in MII or reference clock rising edge in RMII.
25	TX_D1	input	Transmit data input bit 1; synchronized with TX_CLK rising edge in MII or reference clock rising edge in RMII.
26	TX_D2	input	Transmit data input bit 2; synchronized with TX_CLK rising edge in MII or reference clock rising edge in RMII.
27	TX_D3	input	Transmit data input bit 3; synchronized with TX_CLK rising edge in MII or reference clock rising edge in RMII.
28	COL/LED2/TX_ER/GPIO	output	Collision detection output in MII (low in full-duplex, high when both TX and RX active in half-duplex); configurable as LED2/TX_ER/GPIO via register.
29	CRS/LED3	output	Carrier sense output in MII (high when medium active); configurable as LED3 via register.
30	LED0	output	Link status LED output; indicates link status with optional transmit/receive activity blink per register and strap configuration.
31	CLKOUT/LED1	output	Clock output (Enhanced Mode default); outputs 25MHz reference from XI at power-up, configurable as LED1 via strap, disabled only in deep power down.
32	RST_N	input	Active-low reset input with internal pull-up; minimum 25µs pulse triggers device reset and strap re-scan with internal register reset.
33	GND	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32-EP(5x5)
Category	Interface
Pins	33

CAD (KiCad official)

Symbol: DP83826ERHBT
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: dp83826erhbt-etched.step / dp83826erhbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83826erhbt.step / dp83826erhbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (115 pp, sha256 0ddec6391c36bec1, retrieved 2026-10-01, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF