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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83826ERHBR

Texas Instruments · Global Sourcing Parts · VQFN-32-EP(5x5)

DP83826ERHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ModeSelect	input	Mode selection pin for enhanced mode (NC or pull high to VDDIO) or basic mode (connect to GND); internal pull-up.
2	CEXT	passive	External capacitor connection pin; connect 2nF capacitor to GND for PLL stabilization.
3	VDDA3V3	power_in	Analog power supply input voltage 3.3V with recommended decoupling capacitors.
4	RD_M	input	Differential receive input (minus) for 10BASE-Te and 100BASE-TX PMD interface, auto-configurable per selected mode.
5	RD_P	input	Differential receive input (plus) for 10BASE-Te and 100BASE-TX PMD interface, auto-configurable per selected mode.
6	TD_M	output	Differential transmit output (minus) for 10BASE-Te and 100BASE-TX PMD interface, auto-configurable per selected mode.
7	TD_P	output	Differential transmit output (plus) for 10BASE-Te and 100BASE-TX PMD interface, auto-configurable per selected mode.
8	XO	output	Crystal oscillator output for reference clock; leave floating when CMOS oscillator connected to XI.
9	XI/50MHzIn	input	Crystal oscillator input; requires 25MHz ±50ppm crystal/oscillator in MII or RMII leader mode, or 50MHz ±50ppm CMOS oscillator in RMII follower mode.
10	RBIAS	passive	Bias resistor connection to GND with 6.49kΩ ±1% precision value for internal reference.
11	MDIO	bidirectional	Bidirectional serial management data I/O with 10kΩ internal pull-up; capable of open-drain output for management access.
12	MDC	input	Management data clock input synchronizing MDIO serial interface; maximum clock rate 25MHz with no minimum rate.
13	RX_D3	output	Receive data bit 3 output synchronized to RX_CLK rising edge containing valid data when RX_DV asserted; half-nibble in MII mode or 2-bit in RMII mode.
14	RX_D2	output	Receive data bit 2 output synchronized to RX_CLK rising edge containing valid data when RX_DV asserted; half-nibble in MII mode or 2-bit in RMII mode.
15	RX_D1	output	Receive data bit 1 output synchronized to RX_CLK rising edge containing valid data when RX_DV asserted; half-nibble in MII mode or 2-bit in RMII mode.
16	RX_D0	output	Receive data bit 0 output synchronized to RX_CLK rising edge containing valid data when RX_DV asserted; half-nibble in MII mode or 2-bit in RMII mode.
17	VDDIO	power_in	I/O power supply input voltage 3.3V or 1.8V with recommended decoupling capacitors.
18	RX_DV/CRS_DV	output	Receive data valid output in MII mode or combined carrier sense and RX valid (CRS_DV) in RMII mode; indicates valid data on RX_D[3:0] in MII or RX_D[1:0] in RMII.
19	RX_CLK/50MHz_RMII	output	MII receive clock output at 25MHz for 100Mbps or 2.5MHz for 10Mbps derived from receive data; or 50MHz in RMII leader mode (unused input in RMII follower mode).
20	RX_ER	output	Receive error output synchronized to RX_CLK in MII mode or reference clock in RMII mode indicating error symbols detected in received packets.
21	PWRDN/INT	bidirectional	Power down input (default) or interrupt output when configured via register; active-low open-drain output with 9.5kΩ internal pull-up.
22	TX_CLK	output	MII transmit clock output at 25MHz for 100Mbps or 2.5MHz for 10Mbps with fixed phase to input clock; unused in RMII mode.
23	TX_EN	input	Transmit enable input appearing on TX_CLK rising edge indicating valid transmit data on TX_D[3:0] in MII or TX_D[1:0] in RMII mode; active-high signal.
24	TX_D0	input	Transmit data bit 0 input synchronized to TX_CLK rising edge in MII mode or reference clock edge in RMII mode.
25	TX_D1	input	Transmit data bit 1 input synchronized to TX_CLK rising edge in MII mode or reference clock edge in RMII mode.
26	TX_D2	input	Transmit data bit 2 input synchronized to TX_CLK rising edge in MII mode or reference clock edge in RMII mode.
27	TX_D3	input	Transmit data bit 3 input synchronized to TX_CLK rising edge in MII mode or reference clock edge in RMII mode.
28	COL/LED2/TX_ER/GPIO	output	Collision detection output (default) asserted in half-duplex when both transmit and receive active, configurable as LED2, MII TX_ER, or GPIO via register.
29	CRS/LED3	output	Carrier sense output asserted when transmit or receive medium active in MII mode, configurable as LED3 status output; unused in RMII mode.
30	LED0	output	Link status LED output indicating link state with activity blinking when transmitter or receiver active; polarity auto-detected from external pull configuration.
31	CLKOUT/LED1	output	25MHz reference clock output from XI (default after power-on reset) or LED1 output for 100Mbps link indication; clock unaffected by reset, configurable via strap or register.
32	RST_N	input	Active-low reset input requiring minimum 25µs pulse to force device reset; triggers strap resampling and resets all internal registers to default; internal pull-up.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32-EP(5x5)
Category	Global Sourcing Parts
Pins	33

CAD (KiCad official)

Symbol: DP83826ERHBR
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: dp83826erhbr-etched.step / dp83826erhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83826erhbr.step / dp83826erhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (115 pp, sha256 0ddec6391c36bec1, retrieved 2026-10-01, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF