component
DP83825IRMQR
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Texas Instruments Ethernet Transceivers, HVQFN-24-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DP83825IRMQR
Texas Instruments · Ethernet Transceivers · HVQFN-24-EP(3x3)
DP83825IRMQR from Texas Instruments, in a HVQFN-24-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TX_EN | input | RMII transmit enable, active high, presented on the rising edge of TX_CLK to indicate valid data on TX_D[1:0]. |
| 2 | 50MHzOut/LED2/S (RX_DV_En) | output | Outputs a 50MHz clock in RMII leader mode (default) or drives LED2 in follower mode; can be configured as GPIO by register. |
| 3 | INTR/PWRDN | bidirectional | Power-down by default: an active low signal places the device in power-down; as interrupt it is an open-drain output asserted low with a weak internal 9.5kΩ pullup. |
| 4 | LED0/S (ANEG_Dis) | output | Activity and link LED output, always at 3.3V regardless of VDDIO to avoid external components when operating at VDDIO 1.8V. |
| 5 | RST_N | input | Active low reset input; it must be asserted low for at least 25μs to force a reset and re-scan of the straps. |
| 6 | VDDA3V3 | power_in | Analog supply input at 3.3V (recommended 3V to 3.6V); see Section 8.3 for decoupling requirements. |
| 7 | RD_M | input | Differential receive input (PMD) automatically configured to accept either 10BASE-Te or 100BASE-TX signaling. |
| 8 | RD_P | input | Differential receive input (PMD) automatically configured to accept either 10BASE-Te or 100BASE-TX signaling. |
| 9 | GND | power_in | Ground connection. |
| 10 | TD_M | output | Differential transmit output (PMD) configured for 10BASE-Te or 100BASE-TX signaling based on the PHY configuration. |
| 11 | TD_P | output | Differential transmit output (PMD) configured for 10BASE-Te or 100BASE-TX signaling based on the PHY configuration. |
| 12 | XO | output | Crystal output used for crystal only; it can be left floating when a CMOS-level oscillator drives XI. |
| 13 | XI/50MHzIn | input | Crystal or oscillator input: 25MHz ±50ppm in RMII leader mode, 50MHz ±50ppm CMOS-level oscillator in RMII follower mode. |
| 14 | RBIAS | passive | Requires a 6.49kΩ ±1% bias resistor connected between RBIAS and ground. |
| 15 | MDIO | bidirectional | Management data I/O with internal 10kΩ pullup; an external pullup of up to 2.2kΩ can be added if needed. |
| 16 | MDC | input | Management data clock for MDIO, maximum rate 24MHz with no minimum clock rate. |
| 17 | RX_D1 | output | RMII receive data bit 1, synchronous to the reference clock; valid when RX_DV is asserted. Also the leader/follower mode strap. |
| 18 | RX_D0/S (PhyAdd[0]) | output | RMII receive data bit 0, synchronous to the reference clock; valid when RX_DV is asserted. Also the PHY address strap bit 0. |
| 19 | VDDIO | power_in | I/O supply input at 3.3V or 1.8V (3.3V range 3V to 3.6V; 1.8V range 1.62V to 1.98V). |
| 20 | CRS_DV/S (PhyAdd[1]) | output | RMII carrier sense and receive data valid indication combined on one pin; also the PHY address strap bit 1. |
| 21 | GND | power_in | Ground pin. |
| 22 | RX_ER/S (A-MDIX) | output | RMII receive error output asserted high synchronously to the rising reference clock; not required by the MAC because the PHY corrupts data on error. Also the Auto-MDIX strap. |
| 23 | TX_D0 | input | RMII transmit data bit 0 from the MAC, synchronous to the rising edge of the reference clock. |
| 24 | TX_D1 | input | RMII transmit data bit 1 from the MAC, synchronous to the rising edge of the reference clock. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVQFN-24-EP(3x3) |
| Category | Interface |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog supply voltage | AVDD3V3 | -0.3 | 4 | V | 5 | ||
| IO supply voltage 3V3 | VDDIO3V3 | -0.3 | 4 | V | 5 | ||
| IO supply voltage 1V8 | VDDIO1V8 | -0.3 | 2.1 | V | 5 | ||
| Junction temperature | Tj | 105 | °C | 5 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| MDI pins TD-, TD+, RD-, RD+ voltage | -0.3 | 4 | V | 5 | |||
| MAC interface pins voltage | -0.3 | 4 | V | 5 | |||
| SMI interface pins voltage | -0.3 | 4 | V | 5 | |||
| XI voltage | XI | -0.3 | 4 | V | 5 | ||
| Reset pin voltage | -0.3 | 4 | V | 5 | |||
| Analog supply voltage | AVDD3V3 | 3 | 3.3 | 3.6 | V | 5 | |
| IO supply voltage 3V3 | VDDIO3V3 | 3 | 3.3 | 3.6 | V | 5 | |
| IO supply voltage 1V8 | VDDIO1V8 | 1.62 | 1.8 | 1.98 | V | 5 | |
| Operating free-air temperature (DP83825I) | Ta | -40 | 25 | 85 | C | 5 | |
| Input high-level voltage, 3V3 IO | VIH | 1.7 | V | VDDIO= 3V3+/- 10% | 8 | ||
| Input low-level voltage, 3V3 IO | VIL | 0.8 | V | VDDIO= 3V3+/- 10% | 8 | ||
| Output high-level voltage, 3V3 IO | VOH | 2.4 | V | IoH= -2mA, VDDIO=3V3 +/-10% | 8 | ||
| Output low-level voltage, 3V3 IO | VOL | 0.4 | V | IoL= 2mA, VDDIO=3V3 +/- 10% | 8 | ||
| Output low-level voltage, 1V8 IO | VOL | 0.45 | V | IoL= 2mA, VDDIO=1V8 +/- 10% | 8 | ||
| Input high leakage current | Iih | 15 | uA | TA=-40 TO 85C, VIN=VDDIO | 8 | ||
| Input low leakage current | Iil | 15 | uA | TA=-40 TO 85C, VIN=GND | 8 | ||
| Tri-state output high current | Iozh | -15 | 15 | uA | 8 | ||
| Tri-state output low current | Iozl | -15 | 15 | uA | 8 | ||
| Pull down resistance | R | 8 | 10 | 13 | Kohms | Pull Down | 8 |
| Pull up resistance | R | 8 | 10 | 13 | Kohms | Pull UP | 8 |
| Crystal oscillator load capacitance | 15 | 30 | pF | Crystal oscillator | 8 | ||
| Thermal resistance junction-to-ambient | RθJA | 53.5 | °C/W | 5 | |||
| Thermal resistance junction-to-case (top) | RθJC(top) | 49.6 | °C/W | 5 | |||
| Thermal resistance junction-to-case (bottom) | RθJC(bot) | 28.6 | °C/W | 5 | |||
| Thermal resistance junction-to-board | RθJB | 2.3 | °C/W | 5 | |||
| Junction-to-top characterization parameter | YJT | 28.5 | °C/W | 6 | |||
| Junction-to-board characterization parameter | YJB | 14.9 | °C/W | 6 | |||
| Input capacitance | Cin | 5 | pF | 8 | |||
| Differential output voltage, 100BaseTx idle | 1 | V | 100 Base Tx idle transmission | 6 | |||
| Differential voltage, 10BaseTe data transmission | 1.75 | V | 10BaseTe data transmission | 6 | |||
| Supply current AVDD3V3, power optimized, RMII Leader 100BaseTx | I(AVDD3V3) | 37.5 | mA | RMII Leader (100BaseTx) Traffic = 50% | 6 | ||
| Supply current AVDD3V3, power optimized, RMII Follower 100BaseTx | I(AVDD3V3) | 37.5 | mA | RMII Follower (100BaseTx) Traffic = 50% | 6 | ||
| Supply current VDDIO=3V3, power optimized, RMII Leader 100BaseTx | I(VDDIO=3V3) | 7.5 | mA | RMII Leader (100BaseTx) Traffic = 50% | 6 | ||
| Supply current VDDIO=3V3, power optimized, RMII Follower 100BaseTx | I(VDDIO=3V3) | 3.5 | mA | RMII Follower (100BaseTx) Traffic = 50% | 6 | ||
| Supply current VDDIO=1V8, power optimized, RMII Leader 100BaseTx | I(VDDIO=1V8) | 4.5 | mA | RMII Leader (100BaseTx) Traffic = 50% | 6 | ||
| Supply current VDDIO=1V8, power optimized, RMII Follower 100BaseTx | I(VDDIO=1V8) | 1.6 | mA | RMII Follower (100BaseTx) Traffic = 50% | 6 | ||
| Supply current AVDD3V3, cable reach, RMII Leader 100BaseTx | I(AVDD3V3) | 41 | mA | RMII Leader (100BaseTx) Traffic = 50% | 6 | ||
| Supply current AVDD3V3, cable reach, RMII Leader 100BaseTx | I(AVDD3V3) | 41 | 50 | mA | RMII Leader (100BaseTx) Traffic = 100% | 6 | |
| Supply current AVDD3V3, cable reach, RMII Leader 10BaseTe | I(AVDD3V3) | 28 | mA | RMII Leader (10BaseTe) Traffic = 50% | 6 | ||
| Supply current AVDD3V3, cable reach, RMII Leader 10BaseTe | I(AVDD3V3) | 32 | 40 | mA | RMII Leader (10BaseTe) Traffic = 100% | 6 | |
| Supply current AVDD3V3, cable reach, RMII Follower 100BaseTx | I(AVDD3V3) | 41 | 50 | mA | RMII Follower (100BaseTx) Traffic = 50% | 6 | |
| Supply current AVDD3V3, cable reach, RMII Follower 10BaseTe | I(AVDD3V3) | 28 | mA | RMII Follower (10BaseTe) Traffic = 50% | 6 | ||
| Supply current AVDD3V3, cable reach, RMII Follower 10BaseTe | I(AVDD3V3) | 32 | 40 | mA | RMII Follower (10BaseTe) Traffic = 100% | 6 | |
| Supply current AVDD3V3, 100BaseTx EEE mode | I(AVDD=3V3) | 15.5 | mA | 100 BaseTx link in EEE mode with LPIs ON | 7 | ||
| Supply current AVDD3V3, Deep Power Down | I(AVDD=3V3) | 3.5 | mA | Deep Power Down | 7 | ||
| Supply current AVDD3V3, IEEE Power Down | I(AVDD=3V3) | 4 | mA | IEEE Power Down | 7 | ||
| Supply current AVDD3V3, Active Sleep | I(AVDD=3V3) | 11 | mA | Active Sleep | 7 | ||
| Supply current AVDD3V3, Active but not Link | I(AVDD=3V3) | 37 | mA | Active but not Link | 7 | ||
| Supply current AVDD3V3, RESET | I(AVDD=3V3) | 5.5 | mA | RESET | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-Te standard. Each link pulse is nominally 100ns in duration and transmitted every 16ms in the absence of transmit data. Lin | 30 |
CAD (KiCad official)
- Symbol:
DP83825IRMQR - Footprint:
Package_DFN_QFN:QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm - 3D model: HVQFN-24-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
dp83825irmqr-etched.step/dp83825irmqr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dp83825irmqr.step/dp83825irmqr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (99 pp, sha256
ec16ad2e7f01ede1, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DP83825IRMQR
**Texas Instruments** · Ethernet Transceivers · HVQFN-24-EP(3x3)
DP83825IRMQR from Texas Instruments, in a HVQFN-24-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TX_EN | input | RMII transmit enable, active high, presented on the rising edge of TX_CLK to indicate valid data on TX_D[1:0]. |
| 2 | 50MHzOut/LED2/S (RX_DV_En) | output | Outputs a 50MHz clock in RMII leader mode (default) or drives LED2 in follower mode; can be configured as GPIO by register. |
| 3 | INTR/PWRDN | bidirectional | Power-down by default: an active low signal places the device in power-down; as interrupt it is an open-drain output asserted low with a weak internal 9.5kΩ pullup. |
| 4 | LED0/S (ANEG_Dis) | output | Activity and link LED output, always at 3.3V regardless of VDDIO to avoid external components when operating at VDDIO 1.8V. |
| 5 | RST_N | input | Active low reset input; it must be asserted low for at least 25μs to force a reset and re-scan of the straps. |
| 6 | VDDA3V3 | power_in | Analog supply input at 3.3V (recommended 3V to 3.6V); see Section 8.3 for decoupling requirements. |
| 7 | RD_M | input | Differential receive input (PMD) automatically configured to accept either 10BASE-Te or 100BASE-TX signaling. |
| 8 | RD_P | input | Differential receive input (PMD) automatically configured to accept either 10BASE-Te or 100BASE-TX signaling. |
| 9 | GND | power_in | Ground connection. |
| 10 | TD_M | output | Differential transmit output (PMD) configured for 10BASE-Te or 100BASE-TX signaling based on the PHY configuration. |
| 11 | TD_P | output | Differential transmit output (PMD) configured for 10BASE-Te or 100BASE-TX signaling based on the PHY configuration. |
| 12 | XO | output | Crystal output used for crystal only; it can be left floating when a CMOS-level oscillator drives XI. |
| 13 | XI/50MHzIn | input | Crystal or oscillator input: 25MHz ±50ppm in RMII leader mode, 50MHz ±50ppm CMOS-level oscillator in RMII follower mode. |
| 14 | RBIAS | passive | Requires a 6.49kΩ ±1% bias resistor connected between RBIAS and ground. |
| 15 | MDIO | bidirectional | Management data I/O with internal 10kΩ pullup; an external pullup of up to 2.2kΩ can be added if needed. |
| 16 | MDC | input | Management data clock for MDIO, maximum rate 24MHz with no minimum clock rate. |
| 17 | RX_D1 | output | RMII receive data bit 1, synchronous to the reference clock; valid when RX_DV is asserted. Also the leader/follower mode strap. |
| 18 | RX_D0/S (PhyAdd[0]) | output | RMII receive data bit 0, synchronous to the reference clock; valid when RX_DV is asserted. Also the PHY address strap bit 0. |
| 19 | VDDIO | power_in | I/O supply input at 3.3V or 1.8V (3.3V range 3V to 3.6V; 1.8V range 1.62V to 1.98V). |
| 20 | CRS_DV/S (PhyAdd[1]) | output | RMII carrier sense and receive data valid indication combined on one pin; also the PHY address strap bit 1. |
| 21 | GND | power_in | Ground pin. |
| 22 | RX_ER/S (A-MDIX) | output | RMII receive error output asserted high synchronously to the rising reference clock; not required by the MAC because the PHY corrupts data on error. Also the Auto-MDIX strap. |
| 23 | TX_D0 | input | RMII transmit data bit 0 from the MAC, synchronous to the rising edge of the reference clock. |
| 24 | TX_D1 | input | RMII transmit data bit 1 from the MAC, synchronous to the rising edge of the reference clock. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVQFN-24-EP(3x3) |
| Category | Interface |
| Pins | 25 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog supply voltage | AVDD3V3 | -0.3 | | 4 | V | | 5 |
| IO supply voltage 3V3 | VDDIO3V3 | -0.3 | | 4 | V | | 5 |
| IO supply voltage 1V8 | VDDIO1V8 | -0.3 | | 2.1 | V | | 5 |
| Junction temperature | Tj | | | 105 | °C | | 5 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 5 |
| MDI pins TD-, TD+, RD-, RD+ voltage | | -0.3 | | 4 | V | | 5 |
| MAC interface pins voltage | | -0.3 | | 4 | V | | 5 |
| SMI interface pins voltage | | -0.3 | | 4 | V | | 5 |
| XI voltage | XI | -0.3 | | 4 | V | | 5 |
| Reset pin voltage | | -0.3 | | 4 | V | | 5 |
| Analog supply voltage | AVDD3V3 | 3 | 3.3 | 3.6 | V | | 5 |
| IO supply voltage 3V3 | VDDIO3V3 | 3 | 3.3 | 3.6 | V | | 5 |
| IO supply voltage 1V8 | VDDIO1V8 | 1.62 | 1.8 | 1.98 | V | | 5 |
| Operating free-air temperature (DP83825I) | Ta | -40 | 25 | 85 | C | | 5 |
| Input high-level voltage, 3V3 IO | VIH | 1.7 | | | V | VDDIO= 3V3+/- 10% | 8 |
| Input low-level voltage, 3V3 IO | VIL | | | 0.8 | V | VDDIO= 3V3+/- 10% | 8 |
| Output high-level voltage, 3V3 IO | VOH | 2.4 | | | V | IoH= -2mA, VDDIO=3V3 +/-10% | 8 |
| Output low-level voltage, 3V3 IO | VOL | | | 0.4 | V | IoL= 2mA, VDDIO=3V3 +/- 10% | 8 |
| Output low-level voltage, 1V8 IO | VOL | | | 0.45 | V | IoL= 2mA, VDDIO=1V8 +/- 10% | 8 |
| Input high leakage current | Iih | | | 15 | uA | TA=-40 TO 85C, VIN=VDDIO | 8 |
| Input low leakage current | Iil | | | 15 | uA | TA=-40 TO 85C, VIN=GND | 8 |
| Tri-state output high current | Iozh | -15 | | 15 | uA | | 8 |
| Tri-state output low current | Iozl | -15 | | 15 | uA | | 8 |
| Pull down resistance | R | 8 | 10 | 13 | Kohms | Pull Down | 8 |
| Pull up resistance | R | 8 | 10 | 13 | Kohms | Pull UP | 8 |
| Crystal oscillator load capacitance | | 15 | | 30 | pF | Crystal oscillator | 8 |
| Thermal resistance junction-to-ambient | RθJA | | 53.5 | | °C/W | | 5 |
| Thermal resistance junction-to-case (top) | RθJC(top) | | 49.6 | | °C/W | | 5 |
| Thermal resistance junction-to-case (bottom) | RθJC(bot) | | 28.6 | | °C/W | | 5 |
| Thermal resistance junction-to-board | RθJB | | 2.3 | | °C/W | | 5 |
| Junction-to-top characterization parameter | YJT | | 28.5 | | °C/W | | 6 |
| Junction-to-board characterization parameter | YJB | | 14.9 | | °C/W | | 6 |
| Input capacitance | Cin | | 5 | | pF | | 8 |
| Differential output voltage, 100BaseTx idle | | | 1 | | V | 100 Base Tx idle transmission | 6 |
| Differential voltage, 10BaseTe data transmission | | | 1.75 | | V | 10BaseTe data transmission | 6 |
| Supply current AVDD3V3, power optimized, RMII Leader 100BaseTx | I(AVDD3V3) | | 37.5 | | mA | RMII Leader (100BaseTx) Traffic = 50% | 6 |
| Supply current AVDD3V3, power optimized, RMII Follower 100BaseTx | I(AVDD3V3) | | 37.5 | | mA | RMII Follower (100BaseTx) Traffic = 50% | 6 |
| Supply current VDDIO=3V3, power optimized, RMII Leader 100BaseTx | I(VDDIO=3V3) | | 7.5 | | mA | RMII Leader (100BaseTx) Traffic = 50% | 6 |
| Supply current VDDIO=3V3, power optimized, RMII Follower 100BaseTx | I(VDDIO=3V3) | | 3.5 | | mA | RMII Follower (100BaseTx) Traffic = 50% | 6 |
| Supply current VDDIO=1V8, power optimized, RMII Leader 100BaseTx | I(VDDIO=1V8) | | 4.5 | | mA | RMII Leader (100BaseTx) Traffic = 50% | 6 |
| Supply current VDDIO=1V8, power optimized, RMII Follower 100BaseTx | I(VDDIO=1V8) | | 1.6 | | mA | RMII Follower (100BaseTx) Traffic = 50% | 6 |
| Supply current AVDD3V3, cable reach, RMII Leader 100BaseTx | I(AVDD3V3) | | 41 | | mA | RMII Leader (100BaseTx) Traffic = 50% | 6 |
| Supply current AVDD3V3, cable reach, RMII Leader 100BaseTx | I(AVDD3V3) | | 41 | 50 | mA | RMII Leader (100BaseTx) Traffic = 100% | 6 |
| Supply current AVDD3V3, cable reach, RMII Leader 10BaseTe | I(AVDD3V3) | | 28 | | mA | RMII Leader (10BaseTe) Traffic = 50% | 6 |
| Supply current AVDD3V3, cable reach, RMII Leader 10BaseTe | I(AVDD3V3) | | 32 | 40 | mA | RMII Leader (10BaseTe) Traffic = 100% | 6 |
| Supply current AVDD3V3, cable reach, RMII Follower 100BaseTx | I(AVDD3V3) | | 41 | 50 | mA | RMII Follower (100BaseTx) Traffic = 50% | 6 |
| Supply current AVDD3V3, cable reach, RMII Follower 10BaseTe | I(AVDD3V3) | | 28 | | mA | RMII Follower (10BaseTe) Traffic = 50% | 6 |
| Supply current AVDD3V3, cable reach, RMII Follower 10BaseTe | I(AVDD3V3) | | 32 | 40 | mA | RMII Follower (10BaseTe) Traffic = 100% | 6 |
| Supply current AVDD3V3, 100BaseTx EEE mode | I(AVDD=3V3) | | 15.5 | | mA | 100 BaseTx link in EEE mode with LPIs ON | 7 |
| Supply current AVDD3V3, Deep Power Down | I(AVDD=3V3) | | 3.5 | | mA | Deep Power Down | 7 |
| Supply current AVDD3V3, IEEE Power Down | I(AVDD=3V3) | | 4 | | mA | IEEE Power Down | 7 |
| Supply current AVDD3V3, Active Sleep | I(AVDD=3V3) | | 11 | | mA | Active Sleep | 7 |
| Supply current AVDD3V3, Active but not Link | I(AVDD=3V3) | | 37 | | mA | Active but not Link | 7 |
| Supply current AVDD3V3, RESET | I(AVDD=3V3) | | 5.5 | | mA | RESET | 7 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | | The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-Te standard. Each link pulse is nominally 100ns in duration and transmitted every 16ms in the absence of transmit data. Lin | 30 |
## CAD (KiCad official)
- Symbol: `DP83825IRMQR`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm`
- 3D model: HVQFN-24-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `dp83825irmqr-etched.step` / `dp83825irmqr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83825irmqr.step` / `dp83825irmqr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dp83825i.pdf) (99 pp, sha256 `ec16ad2e7f01ede1`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dp83825irmqr-datasheet.pdf)