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DP83822IRHBT

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Texas Instruments Ethernet Transceivers, HVQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DP83822IRHBT

Texas Instruments · Ethernet Transceivers · HVQFN-32-EP(5x5)

DP83822IRHBT from Texas Instruments, in a HVQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RX_D3/GPIO3 bidirectional Receive data bit 3 in MII/RGMII modes (also PHY_AD4 strap, S-PD), configurable as LED or GPIO3 in RMII mode, and 50 MHz output clock in RMII master mode.
2 TX_CLK bidirectional MII transmit clock output (25 MHz at 100 Mbps, 2.5 MHz at 10 Mbps), Hi-Z in RMII mode, and RGMII transmit clock input with internal pull-down (25 MHz at 100 Mbps, 2.5 MHz at 10 Mbps); driven low as an output during reset.
3 TX_EN/TX_CTRL input Transmit enable (active high, sampled on rising edge of TX_CLK) in MII/RMII, or RGMII transmit control; internal pull-down.
4 TX_D0 input Transmit data bit 0 from the MAC, synchronous to TX_CLK (MII/RGMII) or reference clock (RMII); internal pull-down.
5 TX_D1 input Transmit data bit 1 from the MAC, synchronous to TX_CLK (MII/RGMII) or reference clock (RMII); internal pull-down.
6 TX_D2 input Transmit data bit 2 from the MAC, synchronous to TX_CLK in MII/RGMII modes; internal pull-down.
7 TX_D3 input Transmit data bit 3 from the MAC, synchronous to TX_CLK in MII/RGMII modes; internal pull-down.
8 INT/PWDN_N bidirectional Open-drain interrupt output or active-low power-down input (default is power-down), selected by register, with a weak internal pull-up; an external pull-up may be needed.
9 RD_M input Differential receive input (PMD, analog) auto-configured for 10BASE-Te, 100BASE-TX or 100BASE-FX signaling.
10 RD_P input Differential receive input (PMD, analog) auto-configured for 10BASE-Te, 100BASE-TX or 100BASE-FX signaling.
11 TD_M output Differential transmit output (PMD, analog) auto-configured for 10BASE-Te, 100BASE-TX or 100BASE-FX signaling.
12 TD_P output Differential transmit output (PMD, analog) auto-configured for 10BASE-Te, 100BASE-TX or 100BASE-FX signaling.
13 NC unconnected No connect; leave floating.
14 AVD power_in Analog supply, 3.3 V or 1.8 V.
15 NC unconnected No connect; leave floating.
16 RBIAS passive Bias resistor connection; a 4.87 kΩ ±1% resistor must be connected from RBIAS to GND.
17 LED_0 output Link LED output (default) or link plus TX/RX activity indication; also a 4-level strap pin with internal pull-up (S-PU).
18 RESET_N input Active-low reset input with internal pull-up that reinitializes all internal registers; hold low for at least 10 µs.
19 MDIO bidirectional Bidirectional management data I/O; requires a 2.2 kΩ pull-up resistor.
20 MDC input Management data clock for MDIO, maximum 25 MHz with no minimum rate; internal pull-down.
21 VDDIO power_in I/O supply, 3.3 V, 2.5 V or 1.8 V.
22 XO output Crystal output used only with a crystal; must be left floating when a CMOS-level oscillator drives XI.
23 XI input Crystal/oscillator input: 25 MHz ±100 ppm crystal or oscillator (MII/RGMII/RMII master), or 50 MHz ±100 ppm CMOS oscillator in RMII slave mode.
24 LED_1/GPIO1 bidirectional Speed LED (default tri-state), GPIO1, or 100BASE-FX signal detect input (VDDIO level); strap pin with internal pull-down, may be left floating if unused.
25 RX_CLK output MII/RGMII receive clock (25 MHz at 100 Mbps, 2.5 MHz at 10 Mbps) derived from the received data stream; not used in RMII mode.
26 RX_DV/RX_CTRL output Receive data valid in MII/RMII or RGMII receive control combining RX_DV and RX_ER; strap pin with internal pull-down.
27 CRS/CRS_DV output Carrier sense in MII or carrier sense/receive data valid in RMII; not used in RGMII; strap pin with internal pull-up.
28 RX_ER output Receive error indication in MII and RMII modes (not used in RGMII); strap pin with internal pull-up.
29 COL/GPIO2 bidirectional MII collision detect (always low in full duplex), LED or GPIO2 via register; also PHY_AD0 strap pin with internal pull-up; not used in RMII for collision.
30 RX_D0 output Receive data bit 0 synchronous to RX_CLK; also PHY_AD1 strap pin with internal pull-down.
31 RX_D1 output Receive data bit 1 synchronous to RX_CLK; also PHY_AD2 strap pin with internal pull-down.
32 RX_D2 output Receive data bit 2 (MII/RGMII) synchronous to RX_CLK; also PHY_AD3 strap pin with internal pull-down.
33 GND power_in Ground; exposed thermal pad.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HVQFN-32-EP(5x5)
Category Interface
Pins 33

CAD (KiCad official)

  • Symbol: DP83822IRHBT
  • Footprint: Package_DFN_QFN:HVQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm
  • 3D model: HVQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: dp83822irhbt-etched.step / dp83822irhbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83822irhbt.step / dp83822irhbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (130 pp, sha256 a83a75e6aa9a4729, retrieved 2026-10-03, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF