DP83640TVVX

@@ -53,7 +53,7 @@         "number": "1",         "name": "TX_CLK",         "type": "output",-        "description": "MII transmit clock output, 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, with integrated 50-\u03a9 signal termination."+        "description": "MII transmit clock output, 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, with integrated 50-Ω signal termination."       },       {         "number": "2",@@ -161,13 +161,13 @@         "number": "19",         "name": "ANA33VDD",         "type": "power_in",-        "description": "Analog VDD supply, 3.3 V \u00b10.3 V nominal."+        "description": "Analog VDD supply, 3.3 V ±0.3 V nominal."       },       {         "number": "20",         "name": "VREF",         "type": "power_in",-        "description": "Bias resistor connection point; connect 4.87-k\u03a9 \u00b11% resistor from VREF to GND for proper circuit biasing."+        "description": "Bias resistor connection point; connect 4.87-kΩ ±1% resistor from VREF to GND for proper circuit biasing."       },       {         "number": "21",@@ -221,13 +221,13 @@         "number": "29",         "name": "RESET_N",         "type": "input",-        "description": "Active-low asynchronous reset input with weak internal pullup; minimum 1 \u00b5s assertion initializes device and reloads strap options."+        "description": "Active-low asynchronous reset input with weak internal pullup; minimum 1 µs assertion initializes device and reloads strap options."       },       {         "number": "30",         "name": "MDIO",         "type": "bidirectional",-        "description": "Bi-directional serial management data I/O for register access; requires 1.5-k\u03a9 external pullup resistor or internal pullup via CDCTRL1 register bit 3."+        "description": "Bi-directional serial management data I/O for register access; requires 1.5-kΩ external pullup resistor or internal pullup via CDCTRL1 register bit 3."       },       {         "number": "31",@@ -239,7 +239,7 @@         "number": "32",         "name": "IO_VDD",         "type": "power_in",-        "description": "I/O VDD supply, 3.3 V \u00b15% or 2.5 V \u00b15% nominal."+        "description": "I/O VDD supply, 3.3 V ±5% or 2.5 V ±5% nominal."       },       {         "number": "33",@@ -251,7 +251,7 @@         "number": "34",         "name": "X1",         "type": "input",-        "description": "Crystal/oscillator input, 25-MHz \u00b150-ppm source for MII mode or 50-MHz for RMII Slave mode or 25-MHz for RMII Master mode."+        "description": "Crystal/oscillator input, 25-MHz ±50-ppm source for MII mode or 50-MHz for RMII Slave mode or 25-MHz for RMII Master mode."       },       {         "number": "35",@@ -275,31 +275,31 @@         "number": "38",         "name": "RX_CLK",         "type": "output",-        "description": "MII receive clock output, 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode, with integrated 50-\u03a9 signal termination."+        "description": "MII receive clock output, 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode, with integrated 50-Ω signal termination."       },       {         "number": "39",         "name": "RX_DV",         "type": "output",-        "description": "MII receive data valid output asserted high indicating valid data on RXD[3:0]; provides integrated 50-\u03a9 signal termination."+        "description": "MII receive data valid output asserted high indicating valid data on RXD[3:0]; provides integrated 50-Ω signal termination."       },       {         "number": "40",         "name": "CRS/CRS_DV",         "type": "output",-        "description": "MII carrier sense output asserted high for non-idle receive medium; provides integrated 50-\u03a9 signal termination; can be used as LED_CFG strap pin."+        "description": "MII carrier sense output asserted high for non-idle receive medium; provides integrated 50-Ω signal termination; can be used as LED_CFG strap pin."       },       {         "number": "41",         "name": "RX_ER",         "type": "output",-        "description": "MII receive error output asserted high synchronously to RX_CLK for invalid symbols in received packets; provides integrated 50-\u03a9 signal termination; can be used as FX_EN_Z fiber mode enable strap pin."+        "description": "MII receive error output asserted high synchronously to RX_CLK for invalid symbols in received packets; provides integrated 50-Ω signal termination; can be used as FX_EN_Z fiber mode enable strap pin."       },       {         "number": "42",         "name": "COL",         "type": "output",-        "description": "MII collision detect output asserted high in half-duplex modes for simultaneous transmit/receive; provides integrated 50-\u03a9 signal termination; can be used as PHYAD0 PHY address strap pin."+        "description": "MII collision detect output asserted high in half-duplex modes for simultaneous transmit/receive; provides integrated 50-Ω signal termination; can be used as PHYAD0 PHY address strap pin."       },       {         "number": "43",@@ -335,7 +335,7 @@         "number": "48",         "name": "IO_VDD",         "type": "power_in",-        "description": "I/O VDD supply, 3.3 V \u00b15% or 2.5 V \u00b15% nominal."+        "description": "I/O VDD supply, 3.3 V ±5% or 2.5 V ±5% nominal."       }     ],     "provenance": {@@ -372,6 +372,46 @@     "viewers": {       "symbol": "viewers/symbol.html",       "footprint": "viewers/footprint.html"-    }+    },+    "models_3d": [+      {+        "file": "dp83640tvvx.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          9.0,+          9.0,+          1.5+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "9dea352d93177c2904afd7d7b68ea8855ce1ab691f69f8b3e13655600514b6bf",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "dp83640tvvx-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          9.0,+          9.0,+          1.5+        ],+        "zmin_mm": -0.0,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "2ac40c66db7952fcf44507e5ef0b99788944bb03193ae67c121ec0106626d159",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]   }-}\ No newline at end of file+}