Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Download PDF

Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83640TVVX

Texas Instruments · Ethernet Transceivers · LQFP-48(7x7)

DP83640TVVX from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TX_CLK	output	MII transmit clock output, 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, with integrated 50-Ω signal termination.
2	TX_EN	input	MII transmit enable active-high input indicating valid data on TXD[3:0]; RMII mode uses TXD[1:0].
3	TXD_0	input	MII transmit data input, accepts data synchronous to TX_CLK.
4	TXD_1	input	MII transmit data input, accepts data synchronous to TX_CLK.
5	TXD_2	input	MII transmit data input, accepts data synchronous to TX_CLK.
6	TXD_3	input	MII transmit data input TXD[3]; RMII transmit data input TXD[1]; can be used as RMII_MAS strap pin.
7	PWRDOWN/INTN	input	Active-low power down input; can be programmed as active-low interrupt output via MICR register.
8	TCK	input	JTAG test clock input with weak internal pullup; maximum rate 25 MHz.
9	TDO	output	JTAG test data output; can also function as GPIO10 for general-purpose I/O.
10	TMS	input	JTAG test mode select input with weak internal pullup.
11	TRST#	input	JTAG active-low asynchronous test reset input with weak internal pullup.
12	TDI	input	JTAG test data input with weak internal pullup; can also function as GPIO11 for general-purpose I/O.
13	RD-	bidirectional	Differential receive input (PMD input pair) configured for 100BASE-TX or 10BASE-T signaling; can be transmit output in Auto-MDIX mode or 100BASE-FX receive in fiber mode; requires 3.3-V bias.
14	RD+	bidirectional	Differential receive input (PMD input pair) configured for 100BASE-TX or 10BASE-T signaling; can be transmit output in Auto-MDIX mode or 100BASE-FX receive in fiber mode; requires 3.3-V bias.
15	CD_VSS	power_in	Analog ground for common-mode driver circuit.
16	TD-	bidirectional	Differential transmit output (PMD output pair) configured for 10BASE-T or 100BASE-TX signaling; can be receive input in Auto-MDIX mode or 100BASE-FX transmit in fiber mode; requires 3.3-V bias.
17	TD+	bidirectional	Differential transmit output (PMD output pair) configured for 10BASE-T or 100BASE-TX signaling; can be receive input in Auto-MDIX mode or 100BASE-FX transmit in fiber mode; requires 3.3-V bias.
18	ANAVSS	power_in	Analog ground for bias and driver circuits.
19	ANA33VDD	power_in	Analog VDD supply, 3.3 V ±0.3 V nominal.
20	VREF	power_in	Bias resistor connection point; connect 4.87-kΩ ±1% resistor from VREF to GND for proper circuit biasing.
21	GPIO1	bidirectional	General-purpose I/O for IEEE 1588 event triggering or capture; CLK_OUT_EN strap pin for enabling clock output.
22	GPIO2	bidirectional	General-purpose I/O for IEEE 1588 event triggering or capture; PCF_EN strap pin for PHY control frame enable.
23	GPIO3	bidirectional	General-purpose I/O for IEEE 1588 event triggering or capture.
24	CLK_OUT	bidirectional	Configurable clock output providing internal PTP clock (25 MHz default), 50-MHz RMII reference, 25-MHz receive clock, or reference pass-through; can input external IEEE 1588 reference clock.
25	GPIO4	bidirectional	General-purpose I/O for IEEE 1588 event triggering or capture.
26	LED_ACT	output	LED output indicating activity in Mode 1, collision in Mode 2, or full-duplex status in Mode 3; can be used as GPIO5.
27	LED_SPEED/FX_SD	bidirectional	LED output showing 10/100 Mb/s speed (ON at 100 Mb/s, OFF at 10 Mb/s); can function as GPIO6 or FX_SD fiber-mode signal detect input.
28	LED_LINK	output	LED output indicating link status; can be used as GPIO7 for general-purpose I/O or AN_EN auto-negotiation enable strap pin.
29	RESET_N	input	Active-low asynchronous reset input with weak internal pullup; minimum 1 µs assertion initializes device and reloads strap options.
30	MDIO	bidirectional	Bi-directional serial management data I/O for register access; requires 1.5-kΩ external pullup resistor or internal pullup via CDCTRL1 register bit 3.
31	MDC	input	Serial management data clock input, synchronous to MDIO, with maximum clock rate of 25 MHz.
32	IO_VDD	power_in	I/O VDD supply, 3.3 V ±5% or 2.5 V ±5% nominal.
33	X2	output	Crystal oscillator output pin for external 25-MHz crystal resonator connection; leave unconnected if using external CMOS oscillator on X1 only.
34	X1	input	Crystal/oscillator input, 25-MHz ±50-ppm source for MII mode or 50-MHz for RMII Slave mode or 25-MHz for RMII Master mode.
35	IO_CORE_VSS	power_in	Digital ground for I/O core circuits.
36	GPIO8	bidirectional	General-purpose I/O for IEEE 1588 event triggering or capture.
37	GPIO9	bidirectional	General-purpose I/O for IEEE 1588 event triggering or capture.
38	RX_CLK	output	MII receive clock output, 25 MHz for 100 Mb/s mode or 2.5 MHz for 10 Mb/s mode, with integrated 50-Ω signal termination.
39	RX_DV	output	MII receive data valid output asserted high indicating valid data on RXD[3:0]; provides integrated 50-Ω signal termination.
40	CRS/CRS_DV	output	MII carrier sense output asserted high for non-idle receive medium; provides integrated 50-Ω signal termination; can be used as LED_CFG strap pin.
41	RX_ER	output	MII receive error output asserted high synchronously to RX_CLK for invalid symbols in received packets; provides integrated 50-Ω signal termination; can be used as FX_EN_Z fiber mode enable strap pin.
42	COL	output	MII collision detect output asserted high in half-duplex modes for simultaneous transmit/receive; provides integrated 50-Ω signal termination; can be used as PHYAD0 PHY address strap pin.
43	RXD_3	output	MII receive data output driven synchronously to RX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s); can be used as PHYAD1 PHY address strap pin.
44	RXD_2	output	MII receive data output driven synchronously to RX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s); can be used as PHYAD2 PHY address strap pin.
45	RXD_1	output	MII receive data output driven synchronously to RX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s); can be used as PHYAD3 PHY address strap pin.
46	RXD_0	output	MII receive data output driven synchronously to RX_CLK (25 MHz for 100 Mb/s, 2.5 MHz for 10 Mb/s); has weak internal pullup; can be used as PHYAD4 PHY address strap pin.
47	IO_VSS	power_in	Digital ground for I/O interface circuits.
48	IO_VDD	power_in	I/O VDD supply, 3.3 V ±5% or 2.5 V ±5% nominal.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-48(7x7)
Category	Interface
Pins	48

CAD (KiCad official)

Symbol: DP83640TVVX
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: dp83640tvvx-etched.step / dp83640tvvx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83640tvvx.step / dp83640tvvx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (136 pp, sha256 dba00c9035801e90, retrieved 2026-09-24, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF