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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83640TVV

Texas Instruments · Ethernet Transceivers · LQFP-48(7x7)

DP83640TVV from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TX_CLK	output	MII transmit clock output at 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, derived from the 25-MHz reference, and in RMII Master mode it outputs the internal 50-MHz reference clock.
2	TX_EN	input	Active-high transmit enable indicating valid data on TXD[3:0] in MII mode or on TXD[1:0] in RMII mode, with an internal pulldown.
3	TXD_0	input	MII transmit data bit 0, sampled synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s), and RMII TXD[0] synchronous to the 50-MHz reference clock.
4	TXD_1	input	MII transmit data bit 1, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s), and RMII TXD[1] synchronous to the 50-MHz reference clock.
5	TXD_2	input	MII transmit data bit 2, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s); RMII uses only TXD[1:0].
6	TXD_3	input	MII transmit data bit 3, synchronous to TX_CLK; this pin also serves as the RMII_MASTER strap with an internal pulldown, enabling RMII Master mode when MII_MODE is strapped high.
7	PWRDOWN/INTN	input	Power-down input that enters Power Down mode when asserted low (weak internal pullup, overdriven by external drive), or an active-low interrupt output when INT_OE is set in MICR.
8	TCK	input	JTAG test clock input with a weak internal pullup.
9	TDO	output	JTAG test data output, which can also be used as GPIO10 when JTAG is not in use.
10	TMS	input	JTAG test mode select input with a weak internal pullup.
11	TRST#	input	Active-low JTAG test reset input with a weak internal pullup.
12	TDI	input	JTAG test data input with a weak internal pullup, which can also be used as GPIO11.
13	RD-	bidirectional	Differential receive input pair (negative), automatically configured for 10BASE-T or 100BASE-TX, requiring 3.3-V bias for operation.
14	RD+	bidirectional	Differential receive input pair (positive), automatically configured for 10BASE-T or 100BASE-TX, requiring 3.3-V bias for operation.
15	CD_VSS	power_in	Analog ground for the 10BASE-T/100BASE-TX common driver.
16	TD-	bidirectional	Differential transmit output pair (negative), automatically configured for 10BASE-T or 100BASE-TX, requiring 3.3-V bias for operation.
17	TD+	bidirectional	Differential transmit output pair (positive), automatically configured for 10BASE-T or 100BASE-TX, requiring 3.3-V bias for operation.
18	ANAVSS	power_in	Analog ground.
19	ANA33VDD	power_in	Analog VDD supply at 3.3 V ±10% (3.3 ± 0.3 V).
20	VREF	power_in	Bias resistor connection, where a 4.87-kΩ 1% resistor must be connected from VREF to GND.
21	GPIO1	bidirectional	General-purpose I/O used to signal or detect events (internal pulldown), which is also the CLK_OUT_EN strap sampled at power-up.
22	GPIO2	bidirectional	General-purpose I/O used to signal or detect events (internal pulldown), which is also the PCF_EN strap enabling response to PHY Control Frames when high.
23	GPIO3	bidirectional	General-purpose I/O used to signal or detect events (internal pulldown).
24	CLK_OUT	bidirectional	Configurable system clock output (default 25 MHz relative to the internal PTP clock) that doubles as an external IEEE 1588 reference clock input, where CLK_OUT_EN should be disabled to avoid contention.
25	GPIO4	bidirectional	General-purpose I/O used to signal or detect events (internal pulldown).
26	LED_ACT	bidirectional	Activity LED output (ON for transmit or receive activity in Mode 1, collision in Mode 2, duplex in Mode 3), which also serves as the AN0 strap input and GPIO5.
27	LED_SPEED/FX_SD	bidirectional	Speed LED that is ON at 100 Mb/s and OFF at 10 Mb/s, which also serves as the FX_SD fiber signal-detect input in 100BASE-FX mode and the AN1 strap.
28	LED_LINK	bidirectional	Link LED that is ON for good link in all modes and blinks for activity in Modes 2 and 3, which also serves as the AN_EN strap and GPIO7.
29	RESET_N	input	Active-low reset with weak internal pullup, where asserting low for at least 1 µs re-initializes all registers and strap options to their defaults.
30	MDIO	bidirectional	Bidirectional management data I/O that requires a 1.5-kΩ pullup resistor, or an internal pullup enabled by CDCTRL1 bit 3.
31	MDC	input	Management data clock input with a maximum rate of 25 MHz and no minimum rate.
32	IO_VDD	power_in	I/O VDD supply (2.5 V or 3.3 V I/O).
33	X2	output	Crystal output for an external 25-MHz crystal resonator, which must be left unconnected when an external CMOS oscillator is used.
34	X1	input	Primary clock reference input requiring a 25-MHz ±50 ppm crystal or CMOS oscillator (50-MHz ±50 ppm CMOS oscillator in RMII Slave mode).
35	IO_CORE_VSS	power_in	Digital ground.
36	GPIO8	bidirectional	General-purpose I/O used to signal or detect events (internal pulldown).
37	GPIO9	bidirectional	General-purpose I/O used to signal or detect events.
38	RX_CLK	output	MII receive clock providing 25 MHz recovered clock in 100 Mb/s mode and 2.5 MHz in 10 Mb/s mode, and in RMII Master mode outputs the internal 50-MHz reference clock.
39	RX_DV	output	Receive data valid asserted high to indicate valid data on RXD[3:0] in MII mode, or RMII receive data valid independent of carrier sense; has an internal pulldown.
40	CRS/CRS_DV	bidirectional	MII carrier sense asserted high when the receive medium is non-idle, or RMII combined carrier sense/receive data valid, which also serves as the LED_CFG strap.
41	RX_ER	bidirectional	Receive error asserted high synchronously to RX_CLK for an invalid symbol in 100 Mb/s MII mode, or to X1 on a media error in RMII mode, which also serves as the FX_EN_Z strap.
42	COL	bidirectional	Collision detect asserted high during collisions in half-duplex 10 and 100 Mb/s modes, always low in full duplex, which also serves as the PHYAD0 strap.
43	RXD_3	bidirectional	MII receive data bit 3 driven synchronously to RX_CLK and valid while RX_DV is asserted, which also serves as the PHYAD1 strap with an internal pulldown.
44	RXD_2	bidirectional	MII receive data bit 2 driven synchronously to RX_CLK and valid while RX_DV is asserted, which also serves as the PHYAD2 strap with an internal pulldown.
45	RXD_1	bidirectional	MII receive data bit 1 driven synchronously to RX_CLK and valid while RX_DV is asserted, which also serves as the PHYAD3 strap with an internal pulldown.
46	RXD_0	bidirectional	MII receive data bit 0 driven synchronously to RX_CLK and valid while RX_DV is asserted, which also serves as the PHYAD4 strap with an internal pulldown.
47	IO_VSS	power_in	Digital ground.
48	IO_VDD	power_in	I/O VDD supply (2.5 V or 3.3 V I/O).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-48(7x7)
Category	Interface
Pins	48

CAD (KiCad official)

Symbol: DP83640TVV
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: dp83640tvv-etched.step / dp83640tvv-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83640tvv.step / dp83640tvv.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (136 pp, sha256 dba00c9035801e90, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF