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DP83630SQE

Texas Instruments · Ethernet Transceivers · WQFN-48-EP(7x7)

DP83630SQE from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TX_CLK	output	MII transmit clock output at 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, which the MAC uses to source TX_EN and TXD[3:0]; in RMII Master mode it outputs the 50 MHz reference clock.
2	TX_EN	input	Active-high MII transmit enable that indicates valid data on TXD[3:0] (TXD[1:0] in RMII mode), with an internal pull-down.
3	TXD_0	input	MII transmit data bit 0, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s mode).
4	TXD_1	input	MII transmit data bit 1, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s mode).
5	TXD_2	input	MII transmit data bit 2, synchronous to TX_CLK (2.5 MHz in 10 Mb/s or 25 MHz in 100 Mb/s mode).
6	TXD_3	input	MII transmit data bit 3, synchronous to TX_CLK; this pin also serves as the RMII_MAS strap (RMII Master enable, effective only when MII_MODE is high) with an internal pull-down.
7	PWRDOWN/INTN	input	Active-low power-down input by default, with weak internal pull-up; it can be configured as an active-low interrupt output (INTN) by setting INT_OE in MICR.
8	TCK	input	JTAG test clock input with a weak internal pull-up.
9	TDO	output	JTAG test data output; the same pin is also available as GPIO10 when JTAG is not used.
10	TMS	input	JTAG test mode select input with a weak internal pull-up.
11	TRST#	input	Active-low JTAG test reset input with a weak internal pull-up.
12	TDI	input	JTAG test data input with a weak internal pull-up; the same pin is also available as GPIO11.
13	RD-	bidirectional	Differential receive input (PMD input pair) for 10BASE-T or 100BASE-TX signaling, which becomes the transmit output pair in Auto-MDIX mode and the receive pair in 100BASE-FX mode and requires 3.3 V bias.
14	RD+	bidirectional	Differential receive input (PMD input pair) for 10BASE-T or 100BASE-TX signaling, which becomes the transmit output pair in Auto-MDIX mode and the receive pair in 100BASE-FX mode and requires 3.3 V bias.
15	CD_VSS	power_in	Analog ground for the 10BASE-T common driver.
16	TD-	bidirectional	Differential transmit output (PMD output pair) automatically configured for 10BASE-T or 100BASE-TX signaling, which becomes the 100BASE-FX transmit pair in fiber mode and requires 3.3 V bias.
17	TD+	bidirectional	Differential transmit output (PMD output pair) automatically configured for 10BASE-T or 100BASE-TX signaling, which becomes the 100BASE-FX transmit pair in fiber mode and requires 3.3 V bias.
18	ANAVSS	power_in	Analog ground.
19	ANA33VDD	power_in	Analog VDD supply, specified as 3.3 V ±0.3 V in the recommended operating conditions.
20	VREF	power_in	Bias resistor connection; a 4.87 kΩ 1% resistor must be connected from VREF to GND.
21	GPIO1	bidirectional	General-purpose IEEE 1588 I/O used to signal or detect events, with internal pull-down; it also serves as the CLK_OUT_EN strap, where high enables the CLK_OUT output at power-up.
22	GPIO2	bidirectional	General-purpose IEEE 1588 I/O used to signal or detect events, with internal pull-down; it also serves as the PCF_EN strap, where high enables the device to respond to PHY Control Frames.
23	GPIO3	bidirectional	General-purpose IEEE 1588 I/O used to signal or detect events, including trigger, capture and interrupt functions.
24	CLK_OUT	bidirectional	Configurable system clock output (default 25 MHz relative to the PTP clock), which can also be used as GPIO12 or as an input for an external IEEE 1588 reference clock, in which case the CLK_OUT_EN strap should be disabled.
25	GPIO4	bidirectional	General-purpose IEEE 1588 I/O used to signal or detect events.
26	LED_ACT	bidirectional	Activity LED that is ON when transmit or receive activity is present in Mode 1; it can also be used as GPIO5 and is the AN0 strap pin with a weak pull-up.
27	LED_SPEED/FX_SD	bidirectional	Speed LED that is ON at 100 Mb/s and OFF at 10 Mb/s; it can also be used as GPIO6, the 100BASE-FX Signal Detect input (FX_SD), and the AN1 strap pin.
28	LED_LINK	bidirectional	Link LED that is ON when link is good (Mode 1), with activity blink in Modes 2 and 3; it can also be used as GPIO7 and is the AN_EN strap pin.
29	RESET_N	input	Active-low reset input with an internal pull-up; asserting it low for at least 1 µs forces a reset that re-initializes registers and re-latches straps.
30	MDIO	bidirectional	Management data I/O, which requires a 1.5 kΩ pull-up resistor or the internal pull-up enabled by bit 3 of CDCTRL1.
31	MDC	input	Management data clock for the MDIO serial interface, with a maximum rate of 25 MHz and no minimum rate, and it may be asynchronous to the transmit and receive clocks.
32	IO_VDD	power_in	I/O VDD supply, 3.3 V ±10% or 2.5 V ±5% per the recommended operating conditions.
33	X2	output	Crystal output for an external 25 MHz crystal resonator; it must be left unconnected when an external CMOS oscillator drives X1.
34	X1	input	Primary clock input that must be a 25 MHz ±50 ppm crystal or CMOS oscillator, or a 50 MHz ±50 ppm CMOS oscillator in RMII Slave mode.
35	IO_CORE_VSS	power_in	Digital ground.
36	GPIO8	bidirectional	General-purpose IEEE 1588 I/O used to signal or detect events.
37	GPIO9	bidirectional	General-purpose IEEE 1588 I/O used to signal or detect events.
38	RX_CLK	output	MII receive clock providing 25 MHz recovered clock in 100 Mb/s mode and 2.5 MHz in 10 Mb/s mode; in RMII Master mode it outputs the 50 MHz reference clock, and it is unused in RMII Slave mode.
39	RX_DV	output	MII receive data valid, asserted high when valid data is present on RXD[3:0], with an internal pull-down; in RMII mode it indicates receive data valid independent of carrier sense.
40	CRS/CRS_DV	output	MII carrier sense, asserted high when the receive medium is non-idle, which combines carrier sense and receive data valid in RMII mode; it also serves as the LED_CFG strap pin with a weak pull-up.
41	RX_ER	output	MII receive error, asserted high synchronously to RX_CLK for an invalid symbol in 100 Mb/s mode; it also serves as the FX_EN_Z strap, where an external pull-down enables 100BASE-FX mode.
42	COL	output	MII collision detect, asserted high on collision in 10 and 100 Mb/s half duplex and always 0 in full duplex; it also serves as the PHYAD0 strap pin with a weak pull-up.
43	RXD_3	output	MII receive data bit 3, driven synchronously to RX_CLK and valid when RX_DV is asserted; it also serves as the PHYAD1 strap pin with an internal pull-down (RMII uses RXD[1:0] only).
44	RXD_2	output	MII receive data bit 2, driven synchronously to RX_CLK and valid when RX_DV is asserted; it also serves as the PHYAD2 strap pin with an internal pull-down.
45	RXD_1	output	MII receive data bit 1, driven synchronously to RX_CLK and valid when RX_DV is asserted; it also serves as the PHYAD3 strap pin with an internal pull-down.
46	RXD_0	output	MII receive data bit 0, driven synchronously to RX_CLK and valid when RX_DV is asserted; it also serves as the PHYAD4 strap pin with an internal pull-down.
47	IO_VSS	power_in	Digital ground.
48	IO_VDD	power_in	I/O VDD supply, 3.3 V ±10% or 2.5 V ±5% per the recommended operating conditions.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-48-EP(7x7)
Category	Interface
Pins	49

CAD (KiCad official)

Symbol: DP83630SQE
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: dp83630sqe-etched.step / dp83630sqe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83630sqe.step / dp83630sqe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (138 pp, sha256 a9aca94ad57ffe39, retrieved 2026-10-10, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF