DP83620SQE

{
  "slug": "dp83620sqe",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Buffers, Drivers, Receivers, Transceivers, WQFN-48-EP(7x7.3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "dp83620sqe",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "dp83620sqe.kicad_sym",
    "dp83620sqe.kicad_mod",
    "dp83620sqe.glb",
    "dp83620sqe.step",
    "dp83620sqe.lbr",
    "docs/hero.png",
    "docs/dp83620sqe-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "dp83620sqe-hero.glb",
    "dp83620sqe-hero.overlay.json",
    "dp83620sqe-etched.glb"
  ],
  "component": {
    "mpn": "DP83620SQE",
    "manufacturer": "Texas Instruments",
    "package": "WQFN-48-EP(7x7.3)",
    "pin_count": 49,
    "category": "Logic",
    "subcategory": "Buffers, Drivers, Receivers, Transceivers",
    "datasheet": "https://www.ti.com/lit/ds/symlink/dp83620.pdf",
    "parts": {
      "symbol": "dp83620sqe.kicad_sym",
      "footprint": "dp83620sqe.kicad_mod",
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      "lbr": "dp83620sqe.lbr"
    },
    "distributor_links": {
      "lcsc": "C2671156"
    },
    "distributor_check": {
      "checked_at": "2026-11-05T21:31:33Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "TX_CLK",
        "type": "output",
        "description": "MII transmit clock output of 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, derived from the 25 MHz reference clock, and an integrated 50 ohm termination is provided."
      },
      {
        "number": "2",
        "name": "TX_EN",
        "type": "input",
        "description": "MII transmit enable input, active high, indicates the presence of valid data on TXD[3:0] (TXD[1:0] in RMII mode)."
      },
      {
        "number": "3",
        "name": "TXD_0",
        "type": "input",
        "description": "MII transmit data bit 0 input, synchronous to TX_CLK; in RMII mode it carries TXD[1:0] synchronous to the 50 MHz reference clock."
      },
      {
        "number": "4",
        "name": "TXD_1",
        "type": "input",
        "description": "MII transmit data bit 1 input, synchronous to TX_CLK; in RMII mode it carries TXD[1:0] synchronous to the 50 MHz reference clock."
      },
      {
        "number": "5",
        "name": "TXD_2",
        "type": "input",
        "description": "MII transmit data bit 2 input, synchronous to TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode)."
      },
      {
        "number": "6",
        "name": "TXD_3",
        "type": "input",
        "description": "MII transmit data bit 3 input with internal pulldown; also serves as the RMII_MAS strap that enables RMII Master mode when MII_MODE is strapped high."
      },
      {
        "number": "7",
        "name": "PWRDOWN/INTN",
        "type": "input",
        "description": "Multiplexed pin that by default is an active low Power Down input, or can be programmed as an active low interrupt output, and has a weak internal pull-up."
      },
      {
        "number": "8",
        "name": "TCK",
        "type": "input",
        "description": "JTAG test clock input with a weak internal pull-up."
      },
      {
        "number": "9",
        "name": "TDO",
        "type": "output",
        "description": "JTAG test data output."
      },
      {
        "number": "10",
        "name": "TMS",
        "type": "input",
        "description": "JTAG test mode select input with a weak internal pull-up."
      },
      {
        "number": "11",
        "name": "TRST#",
        "type": "input",
        "description": "Active low JTAG test reset input with a weak internal pull-up."
      },
      {
        "number": "12",
        "name": "TDI",
        "type": "input",
        "description": "JTAG test data input with a weak internal pull-up."
      },
      {
        "number": "13",
        "name": "RD-",
        "type": "bidirectional",
        "description": "Differential PMD receive input pair (negative), which accepts 100BASE-TX or 10BASE-T signaling and requires 3.3 V bias."
      },
      {
        "number": "14",
        "name": "RD+",
        "type": "bidirectional",
        "description": "Differential PMD receive input pair (positive), which accepts 100BASE-TX or 10BASE-T signaling and requires 3.3 V bias."
      },
      {
        "number": "15",
        "name": "CD_VSS",
        "type": "power_in",
        "description": "Analog ground for the 10BASE-T common driver."
      },
      {
        "number": "16",
        "name": "TD-",
        "type": "bidirectional",
        "description": "Differential PMD transmit output pair (negative), automatically configured for 10BASE-T or 100BASE-TX signaling and requires 3.3 V bias."
      },
      {
        "number": "17",
        "name": "TD+",
        "type": "bidirectional",
        "description": "Differential PMD transmit output pair (positive), automatically configured for 10BASE-T or 100BASE-TX signaling and requires 3.3 V bias."
      },
      {
        "number": "18",
        "name": "ANAVSS",
        "type": "power_in",
        "description": "Analog ground."
      },
      {
        "number": "19",
        "name": "ANA33VDD",
        "type": "power_in",
        "description": "Analog VDD supply, operated at 3.3 V ± 0.3 V."
      },
      {
        "number": "20",
        "name": "VREF",
        "type": "power_in",
        "description": "Bias resistor connection; a 4.87 kΩ 1% resistor should be connected from VREF to GND."
      },
      {
        "number": "21",
        "name": "CLK_OUT_EN",
        "type": "input",
        "description": "CLK_OUT output enable strap with internal pull-down; when high, enables clock output on CLK_OUT at power-up."
      },
      {
        "number": "22",
        "name": "PCF_EN",
        "type": "input",
        "description": "PHY control frame enable strap with internal pull-down; when high, allows the device to respond to PHY Control Frames."
      },
      {
        "number": "23",
        "name": "RESERVED",
        "type": "bidirectional",
        "description": "Reserved pin that should not be connected to external logic; for JTAG implementations it should be tied to GND or VCC through 2.2 kΩ resistors."
      },
      {
        "number": "24",
        "name": "CLK_OUT",
        "type": "output",
        "description": "Configurable system clock output, sourced from the 50 MHz RMII reference in RMII Master mode, the 25 MHz receive clock in 100 Mb mode, or a 25 or 50 MHz pass-through of X1."
      },
      {
        "number": "25",
        "name": "RESERVED",
        "type": "bidirectional",
        "description": "Reserved pin that should not be connected to external logic; for JTAG implementations it should be tied to GND or VCC through 2.2 kΩ resistors."
      },
      {
        "number": "26",
        "name": "LED_ACT",
        "type": "bidirectional",
        "description": "Activity LED (Mode 1) or collision/duplex LED (Mode 2/3) output with strap function for AN0 and a weak internal pull-up."
      },
      {
        "number": "27",
        "name": "LED_SPEED/FX_SD",
        "type": "bidirectional",
        "description": "Speed LED output, ON at 100 Mb/s and OFF at 10 Mb/s, which doubles as the FX_SD fiber signal detect input in 100BASE-FX mode."
      },
      {
        "number": "28",
        "name": "LED_LINK",
        "type": "bidirectional",
        "description": "Link LED output (Mode 1) or link/activity LED (Mode 2 and 3), ON when link is good, with strap function for AN_EN and a weak internal pull-up."
      },
      {
        "number": "29",
        "name": "RESET_N",
        "type": "input",
        "description": "Active low reset input that must be asserted low for at least 1 µs to re-initialize the device and all strap options, with an internal pull-up."
      },
      {
        "number": "30",
        "name": "MDIO",
        "type": "bidirectional",
        "description": "Management data input/output for the serial management interface, which requires a 1.5 kΩ pull-up resistor or an internal pull-up enabled via CDCTRL1 bit 3."
      },
      {
        "number": "31",
        "name": "MDC",
        "type": "input",
        "description": "Management data clock input, with a maximum rate of 25 MHz and no minimum rate."
      },
      {
        "number": "32",
        "name": "IO_VDD",
        "type": "power_in",
        "description": "I/O VDD supply, operated at 3.3 V or 2.5 V."
      },
      {
        "number": "33",
        "name": "X2",
        "type": "output",
        "description": "Crystal output to an external 25 MHz crystal resonator; must be left unconnected if a CMOS oscillator drives X1."
      },
      {
        "number": "34",
        "name": "X1",
        "type": "input",
        "description": "Primary clock reference input that must be a 25 MHz ±50 ppm clock source, or a 50 MHz ±50 ppm CMOS oscillator in RMII Slave mode."
      },
      {
        "number": "35",
        "name": "IO_CORE_VSS",
        "type": "power_in",
        "description": "Digital ground for the core I/O."
      },
      {
        "number": "36",
        "name": "RESERVED",
        "type": "bidirectional",
        "description": "Reserved pin that should not be connected to external logic; for JTAG implementations it should be tied to GND or VCC through 2.2 kΩ resistors."
      },
      {
        "number": "37",
        "name": "RESERVED",
        "type": "bidirectional",
        "description": "Reserved pin that should not be connected to external logic; for JTAG implementations it should be tied to GND or VCC through 2.2 kΩ resistors."
      },
      {
        "number": "38",
        "name": "RX_CLK",
        "type": "output",
        "description": "MII receive clock providing 25 MHz recovered clock for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode, or the 50 MHz RMII reference in RMII Master mode."
      },
      {
        "number": "39",
        "name": "RX_DV",
        "type": "bidirectional",
        "description": "MII receive data valid output asserted high to indicate valid data on RXD[3:0], with internal pulldown and a strap function for MII_MODE."
      },
      {
        "number": "40",
        "name": "CRS/CRS_DV",
        "type": "bidirectional",
        "description": "MII carrier sense output asserted high when the receive medium is non-idle, combined with receive data valid in RMII mode, with a weak internal pull-up and strap function for LED_CFG."
      },
      {
        "number": "41",
        "name": "RX_ER",
        "type": "bidirectional",
        "description": "MII receive error output asserted high to indicate an invalid symbol in 100 Mb/s mode, with a weak internal pull-up and strap function for FX_EN_Z."
      },
      {
        "number": "42",
        "name": "COL",
        "type": "bidirectional",
        "description": "MII collision detect output asserted high on collision in 10 Mb/s and 100 Mb/s half duplex modes, with a weak internal pull-up and strap function for PHYAD0."
      },
      {
        "number": "43",
        "name": "RXD_3",
        "type": "bidirectional",
        "description": "MII receive data bit 3 output driven synchronously to RX_CLK, with internal pulldown and a strap function for PHYAD1."
      },
      {
        "number": "44",
        "name": "RXD_2",
        "type": "bidirectional",
        "description": "MII receive data bit 2 output driven synchronously to RX_CLK, with internal pulldown and a strap function for PHYAD2."
      },
      {
        "number": "45",
        "name": "RXD_1",
        "type": "bidirectional",
        "description": "MII receive data bit 1 output driven synchronously to RX_CLK, with internal pulldown and a strap function for PHYAD3."
      },
      {
        "number": "46",
        "name": "RXD_0",
        "type": "bidirectional",
        "description": "MII receive data bit 0 output driven synchronously to RX_CLK, with internal pulldown and a strap function for PHYAD4."
      },
      {
        "number": "47",
        "name": "IO_VSS",
        "type": "power_in",
        "description": "Digital ground for the I/O."
      },
      {
        "number": "48",
        "name": "IO_VDD",
        "type": "power_in",
        "description": "I/O VDD supply, operated at 3.3 V or 2.5 V."
      },
      {
        "number": "49",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: DP83620SQE is the 250-piece reel ordering variant of the 48-pin WQFN (RHS0048A, 7 mm x 7 mm) package; The DAP has no printed pin number, so it is listed under the name DAP rather than a numeric pin."
        ],
        "pages_sent": 29,
        "cost_usd": 0.0597,
        "at": "2026-11-05T21:31:25"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/dp83620.pdf",
        "pages": 108,
        "sha256": "2fb105d27fcfbe46",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 49,
        "described": 49,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
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        "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",
        "checked": "2026-11-05",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "dp83620sqe-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
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        "sha256": "83496c2359b5c40a01cf29f4d98639e5c137b5fac2858ccd67afcd3b7e25e85a",
        "checked": "2026-11-05",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
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  }
}