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Texas Instruments Buffers, Drivers, Receivers, Transceivers, WQFN-48-EP(7x7.3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DP83620SQE

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · WQFN-48-EP(7x7.3)

DP83620SQE from Texas Instruments, in a WQFN-48-EP(7x7.3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TX_CLK	output	MII transmit clock output of 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, derived from the 25 MHz reference clock, and an integrated 50 ohm termination is provided.
2	TX_EN	input	MII transmit enable input, active high, indicates the presence of valid data on TXD[3:0] (TXD[1:0] in RMII mode).
3	TXD_0	input	MII transmit data bit 0 input, synchronous to TX_CLK; in RMII mode it carries TXD[1:0] synchronous to the 50 MHz reference clock.
4	TXD_1	input	MII transmit data bit 1 input, synchronous to TX_CLK; in RMII mode it carries TXD[1:0] synchronous to the 50 MHz reference clock.
5	TXD_2	input	MII transmit data bit 2 input, synchronous to TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
6	TXD_3	input	MII transmit data bit 3 input with internal pulldown; also serves as the RMII_MAS strap that enables RMII Master mode when MII_MODE is strapped high.
7	PWRDOWN/INTN	input	Multiplexed pin that by default is an active low Power Down input, or can be programmed as an active low interrupt output, and has a weak internal pull-up.
8	TCK	input	JTAG test clock input with a weak internal pull-up.
9	TDO	output	JTAG test data output.
10	TMS	input	JTAG test mode select input with a weak internal pull-up.
11	TRST#	input	Active low JTAG test reset input with a weak internal pull-up.
12	TDI	input	JTAG test data input with a weak internal pull-up.
13	RD-	bidirectional	Differential PMD receive input pair (negative), which accepts 100BASE-TX or 10BASE-T signaling and requires 3.3 V bias.
14	RD+	bidirectional	Differential PMD receive input pair (positive), which accepts 100BASE-TX or 10BASE-T signaling and requires 3.3 V bias.
15	CD_VSS	power_in	Analog ground for the 10BASE-T common driver.
16	TD-	bidirectional	Differential PMD transmit output pair (negative), automatically configured for 10BASE-T or 100BASE-TX signaling and requires 3.3 V bias.
17	TD+	bidirectional	Differential PMD transmit output pair (positive), automatically configured for 10BASE-T or 100BASE-TX signaling and requires 3.3 V bias.
18	ANAVSS	power_in	Analog ground.
19	ANA33VDD	power_in	Analog VDD supply, operated at 3.3 V ± 0.3 V.
20	VREF	power_in	Bias resistor connection; a 4.87 kΩ 1% resistor should be connected from VREF to GND.
21	CLK_OUT_EN	input	CLK_OUT output enable strap with internal pull-down; when high, enables clock output on CLK_OUT at power-up.
22	PCF_EN	input	PHY control frame enable strap with internal pull-down; when high, allows the device to respond to PHY Control Frames.
23	RESERVED	bidirectional	Reserved pin that should not be connected to external logic; for JTAG implementations it should be tied to GND or VCC through 2.2 kΩ resistors.
24	CLK_OUT	output	Configurable system clock output, sourced from the 50 MHz RMII reference in RMII Master mode, the 25 MHz receive clock in 100 Mb mode, or a 25 or 50 MHz pass-through of X1.
25	RESERVED	bidirectional	Reserved pin that should not be connected to external logic; for JTAG implementations it should be tied to GND or VCC through 2.2 kΩ resistors.
26	LED_ACT	bidirectional	Activity LED (Mode 1) or collision/duplex LED (Mode 2/3) output with strap function for AN0 and a weak internal pull-up.
27	LED_SPEED/FX_SD	bidirectional	Speed LED output, ON at 100 Mb/s and OFF at 10 Mb/s, which doubles as the FX_SD fiber signal detect input in 100BASE-FX mode.
28	LED_LINK	bidirectional	Link LED output (Mode 1) or link/activity LED (Mode 2 and 3), ON when link is good, with strap function for AN_EN and a weak internal pull-up.
29	RESET_N	input	Active low reset input that must be asserted low for at least 1 µs to re-initialize the device and all strap options, with an internal pull-up.
30	MDIO	bidirectional	Management data input/output for the serial management interface, which requires a 1.5 kΩ pull-up resistor or an internal pull-up enabled via CDCTRL1 bit 3.
31	MDC	input	Management data clock input, with a maximum rate of 25 MHz and no minimum rate.
32	IO_VDD	power_in	I/O VDD supply, operated at 3.3 V or 2.5 V.
33	X2	output	Crystal output to an external 25 MHz crystal resonator; must be left unconnected if a CMOS oscillator drives X1.
34	X1	input	Primary clock reference input that must be a 25 MHz ±50 ppm clock source, or a 50 MHz ±50 ppm CMOS oscillator in RMII Slave mode.
35	IO_CORE_VSS	power_in	Digital ground for the core I/O.
36	RESERVED	bidirectional	Reserved pin that should not be connected to external logic; for JTAG implementations it should be tied to GND or VCC through 2.2 kΩ resistors.
37	RESERVED	bidirectional	Reserved pin that should not be connected to external logic; for JTAG implementations it should be tied to GND or VCC through 2.2 kΩ resistors.
38	RX_CLK	output	MII receive clock providing 25 MHz recovered clock for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode, or the 50 MHz RMII reference in RMII Master mode.
39	RX_DV	bidirectional	MII receive data valid output asserted high to indicate valid data on RXD[3:0], with internal pulldown and a strap function for MII_MODE.
40	CRS/CRS_DV	bidirectional	MII carrier sense output asserted high when the receive medium is non-idle, combined with receive data valid in RMII mode, with a weak internal pull-up and strap function for LED_CFG.
41	RX_ER	bidirectional	MII receive error output asserted high to indicate an invalid symbol in 100 Mb/s mode, with a weak internal pull-up and strap function for FX_EN_Z.
42	COL	bidirectional	MII collision detect output asserted high on collision in 10 Mb/s and 100 Mb/s half duplex modes, with a weak internal pull-up and strap function for PHYAD0.
43	RXD_3	bidirectional	MII receive data bit 3 output driven synchronously to RX_CLK, with internal pulldown and a strap function for PHYAD1.
44	RXD_2	bidirectional	MII receive data bit 2 output driven synchronously to RX_CLK, with internal pulldown and a strap function for PHYAD2.
45	RXD_1	bidirectional	MII receive data bit 1 output driven synchronously to RX_CLK, with internal pulldown and a strap function for PHYAD3.
46	RXD_0	bidirectional	MII receive data bit 0 output driven synchronously to RX_CLK, with internal pulldown and a strap function for PHYAD4.
47	IO_VSS	power_in	Digital ground for the I/O.
48	IO_VDD	power_in	I/O VDD supply, operated at 3.3 V or 2.5 V.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-48-EP(7x7.3)
Category	Logic
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage	VCC	-0.5		4.2	V		13
Storage Temperature	TSTG	-65		150	°C		13
Maximum Case Temperature				95	°C	TA = 85 °C	13
Maximum Die Temperature	Tj			150	°C		13
ESD Rating				8	kV	RZAP = 1.5k, CZAP = 120 pF	13
DC Input Voltage	VIN	-0.5			V	upper limit VCC + 0.5 V as printed	13
DC Output Voltage	VOUT	-0.5			V	upper limit VCC + 0.5 V as printed	13
Analog Supply Voltage	VCC	-0.3	3.3	0.3	V	nominal 3.3 V, tolerance ±0.3 V as printed	13
I/O Supply Voltage	VI/O	-10		10	%	3.3 V ± 10%	13
I/O Supply Voltage	VI/O	-5		5	%	2.5 V ± 5%	13
Industrial Temperature	TI	-40		85	°C		13
Power Dissipation	PD			290	mW	VI/O = 3.3 V	13
Power Dissipation	PD			260	mW	VI/O = 2.5 V	13
Theta Junction to Case	Tjc			5	°C/W		13
Theta Junction to Ambient	Tja			27.5	°C/W	No Airflow @ 1.0 W	13
Input High Voltage	VIH	2			V		14
Input Low Voltage	VIL			0.8	V	VI/O = 3.3 V	14
Input Low Voltage	VIL			0.7	V	VI/O = 2.5 V	14
Input High Current	IIH			10	µA	VIN = VI/O	14
Input Low Current	IIL			10	µA	VIN = GND	14
Output Low Voltage	VOL			0.4	V	IOL = 4 mA	14
TRI-STATE Output Leakage Current	IOZ	-10		10	µA	VOUT = VI/O or GND	14
PMD Output Pair 100M Transmit Voltage	VTPTD_100	0.95	1	1.05	V		14
PMD Output Pair 100M Transmit Voltage Symmetry	VTPTDsym	-2		2	%		14
PMD Output Pair 10M Transmit Voltage	VTPTD_10	2.2	2.5	2.8	V		14
PMD Output Pair FX 100M Transmit Voltage	VFXTD_100	0.3	0.5	0.93	V		14
CMOS Input Capacitance	CIN1			8	pF		14
CMOS Output Capacitance	COUT1			8	pF		14
100BASE-TX Signal Detect Turn-on Threshold	SDTHon	1000			mV diff	PMD Input Pair, pk-pk	14
Signal Detect Turn-off Threshold	SDTHoff			200	mV diff	PMD Input Pair, pk-pk	14
10BASE-T Receive Threshold	VTH	300		585	mV	PMD Input Pair	14
Supply 100BASE-TX Full Duplex Current	Idd100			88	mA	VCC = 3.3 V, VI/O = 3.3 V, IOUT = 0 mA	14
Supply 100BASE-TX Full Duplex Current	Idd100			84	mA	VCC = 3.3 V, VI/O = 2.5 V, IOUT = 0 mA	14
Supply 10BASE-T Full Duplex Current	Idd10			105	mA	VCC = 3.3 V, VI/O = 3.3 V, IOUT = 0 mA	14
Supply 10BASE-T Full Duplex Current	Idd10			103	mA	VCC = 3.3 V, VI/O = 2.5 V, IOUT = 0 mA	14
Supply Power Down Mode Current	Idd			10	mA	CLK_OUT disabled	14
Bias Resistor VREF to GND			4.87		kΩ	VREF to GND	12
Bias Resistor Tolerance		-1		1	%	1% resistor, VREF to GND	12

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	abs		The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link pulse is nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data.	59

CAD (KiCad official)

Symbol: DP83620SQE
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: WQFN-48-EP(7x7.3) (KiCad packages3D, STEP)
3D model files: dp83620sqe-etched.step / dp83620sqe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83620sqe.step / dp83620sqe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (108 pp, sha256 2fb105d27fcfbe46, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# DP83620SQE

**Texas Instruments** · Buffers, Drivers, Receivers, Transceivers · WQFN-48-EP(7x7.3)

DP83620SQE from Texas Instruments, in a WQFN-48-EP(7x7.3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TX_CLK | output | MII transmit clock output of 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, derived from the 25 MHz reference clock, and an integrated 50 ohm termination is provided. |
| 2 | TX_EN | input | MII transmit enable input, active high, indicates the presence of valid data on TXD[3:0] (TXD[1:0] in RMII mode). |
| 3 | TXD_0 | input | MII transmit data bit 0 input, synchronous to TX_CLK; in RMII mode it carries TXD[1:0] synchronous to the 50 MHz reference clock. |
| 4 | TXD_1 | input | MII transmit data bit 1 input, synchronous to TX_CLK; in RMII mode it carries TXD[1:0] synchronous to the 50 MHz reference clock. |
| 5 | TXD_2 | input | MII transmit data bit 2 input, synchronous to TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode). |
| 6 | TXD_3 | input | MII transmit data bit 3 input with internal pulldown; also serves as the RMII_MAS strap that enables RMII Master mode when MII_MODE is strapped high. |
| 7 | PWRDOWN/INTN | input | Multiplexed pin that by default is an active low Power Down input, or can be programmed as an active low interrupt output, and has a weak internal pull-up. |
| 8 | TCK | input | JTAG test clock input with a weak internal pull-up. |
| 9 | TDO | output | JTAG test data output. |
| 10 | TMS | input | JTAG test mode select input with a weak internal pull-up. |
| 11 | TRST# | input | Active low JTAG test reset input with a weak internal pull-up. |
| 12 | TDI | input | JTAG test data input with a weak internal pull-up. |
| 13 | RD- | bidirectional | Differential PMD receive input pair (negative), which accepts 100BASE-TX or 10BASE-T signaling and requires 3.3 V bias. |
| 14 | RD+ | bidirectional | Differential PMD receive input pair (positive), which accepts 100BASE-TX or 10BASE-T signaling and requires 3.3 V bias. |
| 15 | CD_VSS | power_in | Analog ground for the 10BASE-T common driver. |
| 16 | TD- | bidirectional | Differential PMD transmit output pair (negative), automatically configured for 10BASE-T or 100BASE-TX signaling and requires 3.3 V bias. |
| 17 | TD+ | bidirectional | Differential PMD transmit output pair (positive), automatically configured for 10BASE-T or 100BASE-TX signaling and requires 3.3 V bias. |
| 18 | ANAVSS | power_in | Analog ground. |
| 19 | ANA33VDD | power_in | Analog VDD supply, operated at 3.3 V ± 0.3 V. |
| 20 | VREF | power_in | Bias resistor connection; a 4.87 kΩ 1% resistor should be connected from VREF to GND. |
| 21 | CLK_OUT_EN | input | CLK_OUT output enable strap with internal pull-down; when high, enables clock output on CLK_OUT at power-up. |
| 22 | PCF_EN | input | PHY control frame enable strap with internal pull-down; when high, allows the device to respond to PHY Control Frames. |
| 23 | RESERVED | bidirectional | Reserved pin that should not be connected to external logic; for JTAG implementations it should be tied to GND or VCC through 2.2 kΩ resistors. |
| 24 | CLK_OUT | output | Configurable system clock output, sourced from the 50 MHz RMII reference in RMII Master mode, the 25 MHz receive clock in 100 Mb mode, or a 25 or 50 MHz pass-through of X1. |
| 25 | RESERVED | bidirectional | Reserved pin that should not be connected to external logic; for JTAG implementations it should be tied to GND or VCC through 2.2 kΩ resistors. |
| 26 | LED_ACT | bidirectional | Activity LED (Mode 1) or collision/duplex LED (Mode 2/3) output with strap function for AN0 and a weak internal pull-up. |
| 27 | LED_SPEED/FX_SD | bidirectional | Speed LED output, ON at 100 Mb/s and OFF at 10 Mb/s, which doubles as the FX_SD fiber signal detect input in 100BASE-FX mode. |
| 28 | LED_LINK | bidirectional | Link LED output (Mode 1) or link/activity LED (Mode 2 and 3), ON when link is good, with strap function for AN_EN and a weak internal pull-up. |
| 29 | RESET_N | input | Active low reset input that must be asserted low for at least 1 µs to re-initialize the device and all strap options, with an internal pull-up. |
| 30 | MDIO | bidirectional | Management data input/output for the serial management interface, which requires a 1.5 kΩ pull-up resistor or an internal pull-up enabled via CDCTRL1 bit 3. |
| 31 | MDC | input | Management data clock input, with a maximum rate of 25 MHz and no minimum rate. |
| 32 | IO_VDD | power_in | I/O VDD supply, operated at 3.3 V or 2.5 V. |
| 33 | X2 | output | Crystal output to an external 25 MHz crystal resonator; must be left unconnected if a CMOS oscillator drives X1. |
| 34 | X1 | input | Primary clock reference input that must be a 25 MHz ±50 ppm clock source, or a 50 MHz ±50 ppm CMOS oscillator in RMII Slave mode. |
| 35 | IO_CORE_VSS | power_in | Digital ground for the core I/O. |
| 36 | RESERVED | bidirectional | Reserved pin that should not be connected to external logic; for JTAG implementations it should be tied to GND or VCC through 2.2 kΩ resistors. |
| 37 | RESERVED | bidirectional | Reserved pin that should not be connected to external logic; for JTAG implementations it should be tied to GND or VCC through 2.2 kΩ resistors. |
| 38 | RX_CLK | output | MII receive clock providing 25 MHz recovered clock for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode, or the 50 MHz RMII reference in RMII Master mode. |
| 39 | RX_DV | bidirectional | MII receive data valid output asserted high to indicate valid data on RXD[3:0], with internal pulldown and a strap function for MII_MODE. |
| 40 | CRS/CRS_DV | bidirectional | MII carrier sense output asserted high when the receive medium is non-idle, combined with receive data valid in RMII mode, with a weak internal pull-up and strap function for LED_CFG. |
| 41 | RX_ER | bidirectional | MII receive error output asserted high to indicate an invalid symbol in 100 Mb/s mode, with a weak internal pull-up and strap function for FX_EN_Z. |
| 42 | COL | bidirectional | MII collision detect output asserted high on collision in 10 Mb/s and 100 Mb/s half duplex modes, with a weak internal pull-up and strap function for PHYAD0. |
| 43 | RXD_3 | bidirectional | MII receive data bit 3 output driven synchronously to RX_CLK, with internal pulldown and a strap function for PHYAD1. |
| 44 | RXD_2 | bidirectional | MII receive data bit 2 output driven synchronously to RX_CLK, with internal pulldown and a strap function for PHYAD2. |
| 45 | RXD_1 | bidirectional | MII receive data bit 1 output driven synchronously to RX_CLK, with internal pulldown and a strap function for PHYAD3. |
| 46 | RXD_0 | bidirectional | MII receive data bit 0 output driven synchronously to RX_CLK, with internal pulldown and a strap function for PHYAD4. |
| 47 | IO_VSS | power_in | Digital ground for the I/O. |
| 48 | IO_VDD | power_in | I/O VDD supply, operated at 3.3 V or 2.5 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-48-EP(7x7.3) |
| Category | Logic |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | -0.5 |  | 4.2 | V |  | 13 |
| Storage Temperature | TSTG | -65 |  | 150 | °C |  | 13 |
| Maximum Case Temperature |  |  |  | 95 | °C | TA = 85 °C | 13 |
| Maximum Die Temperature | Tj |  |  | 150 | °C |  | 13 |
| ESD Rating |  |  |  | 8 | kV | RZAP = 1.5k, CZAP = 120 pF | 13 |
| DC Input Voltage | VIN | -0.5 |  |  | V | upper limit VCC + 0.5 V as printed | 13 |
| DC Output Voltage | VOUT | -0.5 |  |  | V | upper limit VCC + 0.5 V as printed | 13 |
| Analog Supply Voltage | VCC | -0.3 | 3.3 | 0.3 | V | nominal 3.3 V, tolerance ±0.3 V as printed | 13 |
| I/O Supply Voltage | VI/O | -10 |  | 10 | % | 3.3 V ± 10% | 13 |
| I/O Supply Voltage | VI/O | -5 |  | 5 | % | 2.5 V ± 5% | 13 |
| Industrial Temperature | TI | -40 |  | 85 | °C |  | 13 |
| Power Dissipation | PD |  |  | 290 | mW | VI/O = 3.3 V | 13 |
| Power Dissipation | PD |  |  | 260 | mW | VI/O = 2.5 V | 13 |
| Theta Junction to Case | Tjc |  |  | 5 | °C/W |  | 13 |
| Theta Junction to Ambient | Tja |  |  | 27.5 | °C/W | No Airflow @ 1.0 W | 13 |
| Input High Voltage | VIH | 2 |  |  | V |  | 14 |
| Input Low Voltage | VIL |  |  | 0.8 | V | VI/O = 3.3 V | 14 |
| Input Low Voltage | VIL |  |  | 0.7 | V | VI/O = 2.5 V | 14 |
| Input High Current | IIH |  |  | 10 | µA | VIN = VI/O | 14 |
| Input Low Current | IIL |  |  | 10 | µA | VIN = GND | 14 |
| Output Low Voltage | VOL |  |  | 0.4 | V | IOL = 4 mA | 14 |
| TRI-STATE Output Leakage Current | IOZ | -10 |  | 10 | µA | VOUT = VI/O or GND | 14 |
| PMD Output Pair 100M Transmit Voltage | VTPTD_100 | 0.95 | 1 | 1.05 | V |  | 14 |
| PMD Output Pair 100M Transmit Voltage Symmetry | VTPTDsym | -2 |  | 2 | % |  | 14 |
| PMD Output Pair 10M Transmit Voltage | VTPTD_10 | 2.2 | 2.5 | 2.8 | V |  | 14 |
| PMD Output Pair FX 100M Transmit Voltage | VFXTD_100 | 0.3 | 0.5 | 0.93 | V |  | 14 |
| CMOS Input Capacitance | CIN1 |  |  | 8 | pF |  | 14 |
| CMOS Output Capacitance | COUT1 |  |  | 8 | pF |  | 14 |
| 100BASE-TX Signal Detect Turn-on Threshold | SDTHon | 1000 |  |  | mV diff | PMD Input Pair, pk-pk | 14 |
| Signal Detect Turn-off Threshold | SDTHoff |  |  | 200 | mV diff | PMD Input Pair, pk-pk | 14 |
| 10BASE-T Receive Threshold | VTH | 300 |  | 585 | mV | PMD Input Pair | 14 |
| Supply 100BASE-TX Full Duplex Current | Idd100 |  |  | 88 | mA | VCC = 3.3 V, VI/O = 3.3 V, IOUT = 0 mA | 14 |
| Supply 100BASE-TX Full Duplex Current | Idd100 |  |  | 84 | mA | VCC = 3.3 V, VI/O = 2.5 V, IOUT = 0 mA | 14 |
| Supply 10BASE-T Full Duplex Current | Idd10 |  |  | 105 | mA | VCC = 3.3 V, VI/O = 3.3 V, IOUT = 0 mA | 14 |
| Supply 10BASE-T Full Duplex Current | Idd10 |  |  | 103 | mA | VCC = 3.3 V, VI/O = 2.5 V, IOUT = 0 mA | 14 |
| Supply Power Down Mode Current | Idd |  |  | 10 | mA | CLK_OUT disabled | 14 |
| Bias Resistor VREF to GND |  |  | 4.87 |  | kΩ | VREF to GND | 12 |
| Bias Resistor Tolerance |  | -1 |  | 1 | % | 1% resistor, VREF to GND | 12 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs |  | The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link pulse is nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data. | 59 |

## CAD (KiCad official)

- Symbol: `DP83620SQE`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: WQFN-48-EP(7x7.3) (KiCad packages3D, STEP)
- 3D model files: `dp83620sqe-etched.step` / `dp83620sqe-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83620sqe.step` / `dp83620sqe.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dp83620.pdf) (108 pp, sha256 `2fb105d27fcfbe46`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dp83620sqe-datasheet.pdf)

DP83620SQE

Verified DP83620SQE

Verification log 1 record

DP83620SQE

Pinout

Key specifications

Electrical characteristics

Materials and finish

CAD (KiCad official)

Provenance