DP83620SQ

{
  "slug": "dp83620sq",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Ethernet Transceivers, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface",
    "dp83620sq",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "dp83620sq.kicad_sym",
    "dp83620sq.kicad_mod",
    "dp83620sq.glb",
    "dp83620sq.step",
    "dp83620sq.lbr",
    "docs/hero.png",
    "docs/dp83620sq-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "dp83620sq-hero.glb",
    "dp83620sq-hero.overlay.json",
    "dp83620sq-etched.glb"
  ],
  "component": {
    "mpn": "DP83620SQ",
    "manufacturer": "Texas Instruments",
    "package": "WQFN-48-EP(7x7)",
    "pin_count": 49,
    "category": "Interface",
    "subcategory": "Ethernet Transceivers",
    "datasheet": "https://www.ti.com/lit/ds/symlink/dp83620.pdf",
    "parts": {
      "symbol": "dp83620sq.kicad_sym",
      "footprint": "dp83620sq.kicad_mod",
      "model_3d": "dp83620sq-hero.glb",
      "model_3d_plain": "dp83620sq-etched.glb",
      "model_3d_step": "dp83620sq-etched.step",
      "model_3d_step_plain": "dp83620sq.step",
      "lbr": "dp83620sq.lbr"
    },
    "distributor_links": {
      "lcsc": "C181410"
    },
    "distributor_check": {
      "checked_at": "2026-11-05T22:35:57Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "TX_CLK",
        "type": "output",
        "description": "MII transmit clock output at 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, derived from the 25 MHz reference clock, which the MAC uses to source TX_EN and TXD[3:0]."
      },
      {
        "number": "2",
        "name": "TX_EN",
        "type": "input",
        "description": "MII transmit enable input with internal pulldown, where active high indicates valid data on TXD[3:0]."
      },
      {
        "number": "3",
        "name": "TXD_0",
        "type": "input",
        "description": "MII transmit data bit 0 input, sampled synchronous to TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode)."
      },
      {
        "number": "4",
        "name": "TXD_1",
        "type": "input",
        "description": "MII transmit data bit 1 input, sampled synchronous to TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode)."
      },
      {
        "number": "5",
        "name": "TXD_2",
        "type": "input",
        "description": "MII transmit data bit 2 input, sampled synchronous to TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode)."
      },
      {
        "number": "6",
        "name": "TXD_3",
        "type": "input",
        "description": "MII transmit data bit 3 input with internal pulldown, sampled synchronous to TX_CLK; also the RMII_MAS strap option pin."
      },
      {
        "number": "7",
        "name": "PWRDOWN/INTN",
        "type": "input",
        "description": "Active-low power down input (default function) with internal pull-up, which may be reprogrammed as an active-low interrupt output."
      },
      {
        "number": "8",
        "name": "TCK",
        "type": "input",
        "description": "JTAG test clock input with a weak internal pullup."
      },
      {
        "number": "9",
        "name": "TDO",
        "type": "output",
        "description": "JTAG test data output."
      },
      {
        "number": "10",
        "name": "TMS",
        "type": "input",
        "description": "JTAG test mode select input with a weak internal pullup."
      },
      {
        "number": "11",
        "name": "TRST#",
        "type": "input",
        "description": "Active-low JTAG test reset input with a weak internal pullup."
      },
      {
        "number": "12",
        "name": "TDI",
        "type": "input",
        "description": "JTAG test data input with a weak internal pullup."
      },
      {
        "number": "13",
        "name": "RD-",
        "type": "bidirectional",
        "description": "Differential receive input (PMD input pair, negative), automatically configured for 100BASE-TX or 10BASE-T signaling and requiring 3.3 V bias."
      },
      {
        "number": "14",
        "name": "RD+",
        "type": "bidirectional",
        "description": "Differential receive input (PMD input pair, positive), automatically configured for 100BASE-TX or 10BASE-T signaling and requiring 3.3 V bias."
      },
      {
        "number": "15",
        "name": "CD_VSS",
        "type": "power_in",
        "description": "Analog ground for the common driver circuitry."
      },
      {
        "number": "16",
        "name": "TD-",
        "type": "bidirectional",
        "description": "Differential transmit output (PMD output pair, negative), automatically configured for 10BASE-T or 100BASE-TX signaling and requiring 3.3 V bias."
      },
      {
        "number": "17",
        "name": "TD+",
        "type": "bidirectional",
        "description": "Differential transmit output (PMD output pair, positive), automatically configured for 10BASE-T or 100BASE-TX signaling and requiring 3.3 V bias."
      },
      {
        "number": "18",
        "name": "ANAVSS",
        "type": "power_in",
        "description": "Analog ground."
      },
      {
        "number": "19",
        "name": "ANA33VDD",
        "type": "power_in",
        "description": "Analog VDD supply, specified as 3.3 V ±0.3 V."
      },
      {
        "number": "20",
        "name": "VREF",
        "type": "power_in",
        "description": "Bias resistor connection, where a 4.87 kOhm 1% resistor must be connected from VREF to GND."
      },
      {
        "number": "21",
        "name": "CLK_OUT_EN",
        "type": "input",
        "description": "Strap input with internal pulldown that, when high, enables clock output on CLK_OUT at power-up."
      },
      {
        "number": "22",
        "name": "PCF_EN",
        "type": "input",
        "description": "Strap input with internal pulldown that, when high, allows the DP83620 to respond to PHY Control Frames."
      },
      {
        "number": "23",
        "name": "RESERVED",
        "type": "unconnected",
        "description": "Reserved pin; should not be connected to external logic, or connected through 2.2 kOhm resistors to GND or VCC for JTAG implementations."
      },
      {
        "number": "24",
        "name": "CLK_OUT",
        "type": "output",
        "description": "Configurable system clock output, sourced from the 50 MHz RMII reference in RMII Master mode, the 25 MHz receive clock in 100 Mb mode, or a 25 MHz or 50 MHz pass-through of X1."
      },
      {
        "number": "25",
        "name": "RESERVED",
        "type": "unconnected",
        "description": "Reserved pin; should not be connected to external logic, or connected through 2.2 kOhm resistors to GND or VCC for JTAG implementations."
      },
      {
        "number": "26",
        "name": "LED_ACT",
        "type": "output",
        "description": "Activity LED driver output (Mode 1) or collision/duplex LED output (Modes 2 and 3), with internal pullup."
      },
      {
        "number": "27",
        "name": "LED_SPEED/FX_SD",
        "type": "output",
        "description": "Speed LED output that is ON at 100 Mb/s and OFF at 10 Mb/s; in 100BASE-FX mode this pin serves as the FX signal detect input."
      },
      {
        "number": "28",
        "name": "LED_LINK",
        "type": "output",
        "description": "Link LED output that is ON when link is good, with activity indication added in Modes 2 and 3."
      },
      {
        "number": "29",
        "name": "RESET_N",
        "type": "input",
        "description": "Active-low reset input with internal pullup that must be asserted low for at least 1 µs to force a reset."
      },
      {
        "number": "30",
        "name": "MDIO",
        "type": "bidirectional",
        "description": "Management data I/O line that requires a 1.5 kOhm pullup resistor, or an internal pullup enabled via CDCTRL1 bit 3."
      },
      {
        "number": "31",
        "name": "MDC",
        "type": "input",
        "description": "Management data clock input with a maximum rate of 25 MHz and no minimum rate."
      },
      {
        "number": "32",
        "name": "IO_VDD",
        "type": "power_in",
        "description": "I/O VDD supply, specified as 3.3 V ±10% or 2.5 V ±5%."
      },
      {
        "number": "33",
        "name": "X2",
        "type": "output",
        "description": "Crystal output for an external 25 MHz crystal resonator, left unconnected when an external CMOS oscillator is used."
      },
      {
        "number": "34",
        "name": "X1",
        "type": "input",
        "description": "Primary clock reference input that must be a 25 MHz ±50 ppm clock source (or 50 MHz CMOS oscillator in RMII Slave mode)."
      },
      {
        "number": "35",
        "name": "IO_CORE_VSS",
        "type": "power_in",
        "description": "Digital ground for the core I/O circuitry."
      },
      {
        "number": "36",
        "name": "RESERVED",
        "type": "unconnected",
        "description": "Reserved pin; should not be connected to external logic, or connected through 2.2 kOhm resistors to GND or VCC for JTAG implementations."
      },
      {
        "number": "37",
        "name": "RESERVED",
        "type": "unconnected",
        "description": "Reserved pin; should not be connected to external logic, or connected through 2.2 kOhm resistors to GND or VCC for JTAG implementations."
      },
      {
        "number": "38",
        "name": "RX_CLK",
        "type": "output",
        "description": "MII receive clock output providing 25 MHz recovered clock in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode."
      },
      {
        "number": "39",
        "name": "RX_DV",
        "type": "output",
        "description": "MII receive data valid output with internal pulldown, asserted high when valid data is present on RXD[3:0]."
      },
      {
        "number": "40",
        "name": "CRS/CRS_DV",
        "type": "output",
        "description": "MII carrier sense output asserted high when the receive medium is non-idle, combined with receive data valid in RMII mode."
      },
      {
        "number": "41",
        "name": "RX_ER",
        "type": "output",
        "description": "MII receive error output asserted high synchronously to RX_CLK when an invalid symbol is detected in a packet in 100 Mb/s mode; also the FX_EN_Z strap pin."
      },
      {
        "number": "42",
        "name": "COL",
        "type": "output",
        "description": "MII collision detect output asserted high on collision in 10 Mb/s and 100 Mb/s half duplex, and held at logic 0 in full duplex."
      },
      {
        "number": "43",
        "name": "RXD_3",
        "type": "output",
        "description": "MII receive data bit 3 output driven synchronously to RX_CLK, valid when RX_DV is asserted; also the PHYAD1 strap pin."
      },
      {
        "number": "44",
        "name": "RXD_2",
        "type": "output",
        "description": "MII receive data bit 2 output driven synchronously to RX_CLK, valid when RX_DV is asserted; also the PHYAD2 strap pin."
      },
      {
        "number": "45",
        "name": "RXD_1",
        "type": "output",
        "description": "MII receive data bit 1 output driven synchronously to RX_CLK, valid when RX_DV is asserted; also the PHYAD3 strap pin."
      },
      {
        "number": "46",
        "name": "RXD_0",
        "type": "output",
        "description": "MII receive data bit 0 output driven synchronously to RX_CLK, valid when RX_DV is asserted; also the PHYAD4 strap pin."
      },
      {
        "number": "47",
        "name": "IO_VSS",
        "type": "power_in",
        "description": "Digital ground for the I/O circuitry."
      },
      {
        "number": "48",
        "name": "IO_VDD",
        "type": "power_in",
        "description": "I/O VDD supply, specified as 3.3 V ±10% or 2.5 V ±5%."
      },
      {
        "number": "49",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin table taken from the RHS0048A package assignment on page 7; the datasheet calls the package 48-p"
        ],
        "pages_sent": 29,
        "cost_usd": 0.0584,
        "at": "2026-11-05T22:35:44"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/dp83620.pdf",
        "pages": 108,
        "sha256": "2fb105d27fcfbe46",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 49,
        "described": 49,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "dp83620sq.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          7.0,
          7.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",
        "checked": "2026-11-05",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "dp83620sq-etched.step",
        "role": "eda",
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        "origin": "footprint origin = pad-pattern centre",
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        "footprint_binding": "identity",
        "sha256": "f8f4ec8905c0bae74692897d6517b755a086793bc9c18166d1b4c291dea7749d",
        "checked": "2026-11-05",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}