# DP83620SQ

**Texas Instruments** · Ethernet Transceivers · WQFN-48-EP(7x7)

DP83620SQ from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TX_CLK | output | MII transmit clock output at 25 MHz in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode, derived from the 25 MHz reference clock, which the MAC uses to source TX_EN and TXD[3:0]. |
| 2 | TX_EN | input | MII transmit enable input with internal pulldown, where active high indicates valid data on TXD[3:0]. |
| 3 | TXD_0 | input | MII transmit data bit 0 input, sampled synchronous to TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode). |
| 4 | TXD_1 | input | MII transmit data bit 1 input, sampled synchronous to TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode). |
| 5 | TXD_2 | input | MII transmit data bit 2 input, sampled synchronous to TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode). |
| 6 | TXD_3 | input | MII transmit data bit 3 input with internal pulldown, sampled synchronous to TX_CLK; also the RMII_MAS strap option pin. |
| 7 | PWRDOWN/INTN | input | Active-low power down input (default function) with internal pull-up, which may be reprogrammed as an active-low interrupt output. |
| 8 | TCK | input | JTAG test clock input with a weak internal pullup. |
| 9 | TDO | output | JTAG test data output. |
| 10 | TMS | input | JTAG test mode select input with a weak internal pullup. |
| 11 | TRST# | input | Active-low JTAG test reset input with a weak internal pullup. |
| 12 | TDI | input | JTAG test data input with a weak internal pullup. |
| 13 | RD- | bidirectional | Differential receive input (PMD input pair, negative), automatically configured for 100BASE-TX or 10BASE-T signaling and requiring 3.3 V bias. |
| 14 | RD+ | bidirectional | Differential receive input (PMD input pair, positive), automatically configured for 100BASE-TX or 10BASE-T signaling and requiring 3.3 V bias. |
| 15 | CD_VSS | power_in | Analog ground for the common driver circuitry. |
| 16 | TD- | bidirectional | Differential transmit output (PMD output pair, negative), automatically configured for 10BASE-T or 100BASE-TX signaling and requiring 3.3 V bias. |
| 17 | TD+ | bidirectional | Differential transmit output (PMD output pair, positive), automatically configured for 10BASE-T or 100BASE-TX signaling and requiring 3.3 V bias. |
| 18 | ANAVSS | power_in | Analog ground. |
| 19 | ANA33VDD | power_in | Analog VDD supply, specified as 3.3 V ±0.3 V. |
| 20 | VREF | power_in | Bias resistor connection, where a 4.87 kOhm 1% resistor must be connected from VREF to GND. |
| 21 | CLK_OUT_EN | input | Strap input with internal pulldown that, when high, enables clock output on CLK_OUT at power-up. |
| 22 | PCF_EN | input | Strap input with internal pulldown that, when high, allows the DP83620 to respond to PHY Control Frames. |
| 23 | RESERVED | unconnected | Reserved pin; should not be connected to external logic, or connected through 2.2 kOhm resistors to GND or VCC for JTAG implementations. |
| 24 | CLK_OUT | output | Configurable system clock output, sourced from the 50 MHz RMII reference in RMII Master mode, the 25 MHz receive clock in 100 Mb mode, or a 25 MHz or 50 MHz pass-through of X1. |
| 25 | RESERVED | unconnected | Reserved pin; should not be connected to external logic, or connected through 2.2 kOhm resistors to GND or VCC for JTAG implementations. |
| 26 | LED_ACT | output | Activity LED driver output (Mode 1) or collision/duplex LED output (Modes 2 and 3), with internal pullup. |
| 27 | LED_SPEED/FX_SD | output | Speed LED output that is ON at 100 Mb/s and OFF at 10 Mb/s; in 100BASE-FX mode this pin serves as the FX signal detect input. |
| 28 | LED_LINK | output | Link LED output that is ON when link is good, with activity indication added in Modes 2 and 3. |
| 29 | RESET_N | input | Active-low reset input with internal pullup that must be asserted low for at least 1 µs to force a reset. |
| 30 | MDIO | bidirectional | Management data I/O line that requires a 1.5 kOhm pullup resistor, or an internal pullup enabled via CDCTRL1 bit 3. |
| 31 | MDC | input | Management data clock input with a maximum rate of 25 MHz and no minimum rate. |
| 32 | IO_VDD | power_in | I/O VDD supply, specified as 3.3 V ±10% or 2.5 V ±5%. |
| 33 | X2 | output | Crystal output for an external 25 MHz crystal resonator, left unconnected when an external CMOS oscillator is used. |
| 34 | X1 | input | Primary clock reference input that must be a 25 MHz ±50 ppm clock source (or 50 MHz CMOS oscillator in RMII Slave mode). |
| 35 | IO_CORE_VSS | power_in | Digital ground for the core I/O circuitry. |
| 36 | RESERVED | unconnected | Reserved pin; should not be connected to external logic, or connected through 2.2 kOhm resistors to GND or VCC for JTAG implementations. |
| 37 | RESERVED | unconnected | Reserved pin; should not be connected to external logic, or connected through 2.2 kOhm resistors to GND or VCC for JTAG implementations. |
| 38 | RX_CLK | output | MII receive clock output providing 25 MHz recovered clock in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode. |
| 39 | RX_DV | output | MII receive data valid output with internal pulldown, asserted high when valid data is present on RXD[3:0]. |
| 40 | CRS/CRS_DV | output | MII carrier sense output asserted high when the receive medium is non-idle, combined with receive data valid in RMII mode. |
| 41 | RX_ER | output | MII receive error output asserted high synchronously to RX_CLK when an invalid symbol is detected in a packet in 100 Mb/s mode; also the FX_EN_Z strap pin. |
| 42 | COL | output | MII collision detect output asserted high on collision in 10 Mb/s and 100 Mb/s half duplex, and held at logic 0 in full duplex. |
| 43 | RXD_3 | output | MII receive data bit 3 output driven synchronously to RX_CLK, valid when RX_DV is asserted; also the PHYAD1 strap pin. |
| 44 | RXD_2 | output | MII receive data bit 2 output driven synchronously to RX_CLK, valid when RX_DV is asserted; also the PHYAD2 strap pin. |
| 45 | RXD_1 | output | MII receive data bit 1 output driven synchronously to RX_CLK, valid when RX_DV is asserted; also the PHYAD3 strap pin. |
| 46 | RXD_0 | output | MII receive data bit 0 output driven synchronously to RX_CLK, valid when RX_DV is asserted; also the PHYAD4 strap pin. |
| 47 | IO_VSS | power_in | Digital ground for the I/O circuitry. |
| 48 | IO_VDD | power_in | I/O VDD supply, specified as 3.3 V ±10% or 2.5 V ±5%. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-48-EP(7x7) |
| Category | Interface |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VCC) | VCC | -0.5 |  | 4.2 | V |  | 13 |
| Storage Temperature | TSTG | -65 |  | 150 | °C |  | 13 |
| Maximum Die Temperature | Tj |  |  | 150 | °C |  | 13 |
| Maximum Case Temperature |  |  |  | 95 | °C | for TA = 85 °C | 13 |
| ESD Rating |  |  | 8 |  | kV | RZAP = 1.5k, CZAP = 120 pF | 13 |
| DC Input Voltage | VIN | -0.5 |  |  | V | printed maximum is VCC + 0.5 V | 13 |
| DC Output Voltage | VOUT | -0.5 |  |  | V | printed maximum is VCC + 0.5 V | 13 |
| Analog Supply Voltage | VCC | -0.3 | 3.3 | 0.3 | V | 3.3 V ± 0.3 V as printed | 13 |
| I/O Supply Voltage tolerance | VI/O | -10 |  | 10 | % | nominal 3.3 V | 13 |
| I/O Supply Voltage tolerance | VI/O | -5 |  | 5 | % | nominal 2.5 V | 13 |
| Industrial Temperature | TI | -40 |  | 85 | °C |  | 13 |
| Power Dissipation (PD) | PD |  |  | 290 | mW | with VI/O = 3.3 V | 13 |
| Power Dissipation (PD) | PD |  |  | 260 | mW | with VI/O = 2.5 V | 13 |
| Theta Junction to Case | Tjc |  |  | 5 | °C / W |  | 13 |
| Theta Junction to Ambient | Tja |  |  | 27.5 | °C / W | No Airflow @ 1.0 W | 13 |
| Input High Voltage | VIH | 2 |  |  | V |  | 14 |
| Input Low Voltage | VIL |  |  | 0.8 | V | VI/O = 3.3 V | 14 |
| Input Low Voltage | VIL |  |  | 0.7 | V | VI/O = 2.5 V | 14 |
| Input High Current | IIH |  |  | 10 | µA | VIN = VI/O | 14 |
| Input Low Current | IIL |  |  | 10 | µA | VIN = GND | 14 |
| Output Low Voltage | VOL |  |  | 0.4 | V | IOL = 4 mA | 14 |
| TRI-STATE Output Leakage Current | IOZ | -10 |  | 10 | µA | VOUT = VI/O or GND | 14 |
| PMD Output Pair 100M Transmit Voltage | VTPTD_100 | 0.95 | 1 | 1.05 | V |  | 14 |
| PMD Output Pair 100M Transmit Voltage Symmetry | VTPTDsym | -2 |  | 2 | % |  | 14 |
| PMD Output Pair 10M Transmit Voltage | VTPTD_10 | 2.2 | 2.5 | 2.8 | V |  | 14 |
| PMD Output Pair FX 100M Transmit Voltage | VFXTD_100 | 0.3 | 0.5 | 0.93 | V |  | 14 |
| 100BASE-TX Signal detect turn-on threshold | SDTHon | 1000 |  |  | mV diff pk-pk | PMD input pair | 14 |
| Signal detect turn-off threshold | SDTHoff |  |  | 200 | mV diff pk-pk | PMD input pair | 14 |
| 10BASE-T Receive Threshold | VTH | 300 |  | 585 | mV | PMD input pair | 14 |
| CMOS Input Capacitance | CIN1 |  | 8 |  | pF |  | 14 |
| CMOS Output Capacitance | COUT1 |  | 8 |  | pF |  | 14 |
| Supply 100BASE-TX (Full Duplex) | Idd100 |  | 88 |  | mA | VCC = 3.3 V, VI/O = 3.3 V, IOUT = 0 mA | 14 |
| Supply 100BASE-TX (Full Duplex) | Idd100 |  | 84 |  | mA | VCC = 3.3 V, VI/O = 2.5 V, IOUT = 0 mA | 14 |
| Supply 10BASE-T (Full Duplex) | Idd10 |  | 105 |  | mA | VCC = 3.3 V, VI/O = 3.3 V, IOUT = 0 mA | 14 |
| Supply 10BASE-T (Full Duplex) | Idd10 |  | 103 |  | mA | VCC = 3.3 V, VI/O = 2.5 V, IOUT = 0 mA | 14 |
| Supply Power Down Mode | Idd |  | 10 |  | mA | CLK_OUT disabled | 14 |
| VREF bias resistor |  |  | 4.87 |  | kΩ | VREF to GND | 12 |
| VREF bias resistor tolerance |  | -1 |  | 1 | % | VREF to GND | 12 |
| MDIO pull-up resistor |  |  | 1.5 |  | kΩ | MDIO pull-up resistor | 47 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs |  | The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link pulse is nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data. | 59 |

## CAD (KiCad official)

- Symbol: `DP83620SQ`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `dp83620sq-etched.step` / `dp83620sq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dp83620sq.step` / `dp83620sq.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/dp83620.pdf) (108 pp, sha256 `2fb105d27fcfbe46`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dp83620sq-datasheet.pdf)