# DMTH8012LPSW-13

**Diodes Incorporated** · MOSFETs · DFN-8(4.9x5.8)

DMTH8012LPSW-13 from Diodes Incorporated, in a DFN-8(4.9x5.8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the N-channel MOSFET, with VDSS rated 80V and continuous ID of 53.7A at TC = +25°C for the device. |
| 2 | S | passive | Source of the N-channel MOSFET, with VDSS rated 80V and continuous ID of 53.7A at TC = +25°C for the device. |
| 3 | S | passive | Source of the N-channel MOSFET, with VDSS rated 80V and continuous ID of 53.7A at TC = +25°C for the device. |
| 4 | G | input | Gate of the N-channel MOSFET, with VGSS rated ±20V and a threshold VGS(TH) of 1V to 3V at ID = 250μA. |
| 5 | D | passive | Drain of the N-channel MOSFET, connected to the exposed drain pad, with VDSS rated 80V and pulsed IDM of 80A. |
| 6 | D | passive | Drain of the N-channel MOSFET, connected to the exposed drain pad, with VDSS rated 80V and pulsed IDM of 80A. |
| 7 | D | passive | Drain of the N-channel MOSFET, connected to the exposed drain pad, with VDSS rated 80V and pulsed IDM of 80A. |
| 8 | D | passive | Drain of the N-channel MOSFET, connected to the exposed drain pad, with VDSS rated 80V and pulsed IDM of 80A. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | DFN-8(4.9x5.8) |
| Category | Transistors |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS |  |  | 80 | V |  | 2 |
| Gate-Source Voltage | VGSS | -20 |  | 20 | V |  | 2 |
| Continuous Drain Current | ID |  |  | 10.3 | A | VGS = 10V, TA = +25C (Note 5) | 2 |
| Continuous Drain Current | ID |  |  | 7.3 | A | VGS = 10V, TA = +100C (Note 5) | 2 |
| Continuous Drain Current | ID |  |  | 53.7 | A | VGS = 10V, TC = +25C (Note 6) | 2 |
| Continuous Drain Current | ID |  |  | 38 | A | VGS = 10V, TC = +100C (Note 6) | 2 |
| Pulsed Drain Current | IDM |  |  | 80 | A | 10μs Pulse, Duty Cycle = 1% | 2 |
| Maximum Continuous Body Diode Forward Current | IS |  |  | 69 | A | Note 6 | 2 |
| Pulsed Body Diode Forward Current | ISM |  |  | 80 | A | 10μs Pulse, Duty Cycle = 1% | 2 |
| Avalanche Current | IAS |  |  | 11.6 | A | L = 0.1mH | 2 |
| Avalanche Energy | EAS |  |  | 6.7 | mJ | L = 0.1mH | 2 |
| Total Power Dissipation | PD |  |  | 3.1 | W | TA = +25°C (Note 5) | 3 |
| Thermal Resistance, Junction to Ambient | RJA |  |  | 49 | °C/W | Note 5 | 3 |
| Total Power Dissipation | PD |  |  | 83.3 | W | TC = +25°C (Note 6) | 3 |
| Thermal Resistance, Junction to Case | RJC |  |  | 1.8 | °C/W | Note 6 | 3 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 |  | 175 | °C |  | 3 |
| Drain-Source Breakdown Voltage | BVDSS | 80 |  |  | V | VGS = 0V, ID = 1mA | 3 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 1 | μA | VDS = 64V, VGS = 0V | 3 |
| Gate-Source Leakage | IGSS | -100 |  | 100 | nA | VGS = ±20V, VDS = 0V | 3 |
| Gate Threshold Voltage | VGS(TH) | 1 |  | 3 | V | VDS = VGS, ID = 250μA | 3 |
| Static Drain-Source On-Resistance | RDS(ON) |  | 14 | 17 | mΩ | VGS = 10V, ID = 12A | 3 |
| Static Drain-Source On-Resistance | RDS(ON) |  | 16.5 | 23.5 | mΩ | VGS = 4.5V, ID = 6A | 3 |
| Diode Forward Voltage | VSD |  | 0.9 | 1.2 | V | VGS = 0V, IS = 20A | 3 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC |  | IF = 12A, di/dt = 100A/μs Body Diode Reverse Recovery Charge QRR, 34.6, nC Notes: 5. Device mounted on FR-4 substrate PC board, 2oz copper, with thermal bias to bottom layer 1inch square copper plat | 3 |
| contacts | Copper | tin | • Terminal Finish, Matte Tin Annealed over Copper Leadframe; | 1 |

## CAD (KiCad official)

- Symbol: `DMTH8012LPSW-13`
- Footprint: `Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm`
- 3D model: DFN-8(4.9x5.8) (KiCad packages3D, STEP)
- 3D model files: `dmth8012lpsw-13-etched.step` / `dmth8012lpsw-13-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmth8012lpsw-13.step` / `dmth8012lpsw-13.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Diodes Incorporated datasheet](https://www.diodes.com/assets/Datasheets/DMTH8012LPSW-13.pdf) (9 pp, sha256 `e4c444aa8e848e27`, retrieved 2026-11-07, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/dmth8012lpsw-13-datasheet.pdf)