component
DMT68M8LSS-13
Public Made by Adomby adom
Diodes Incorporated MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DMT68M8LSS-13
Diodes Incorporated · MOSFETs · SO-8
DMT68M8LSS-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the N-channel MOSFET, tied with pins 2 and 3 to the source. |
| 2 | S | passive | Source of the N-channel MOSFET, tied with pins 1 and 3 to the source. |
| 3 | S | passive | Source of the N-channel MOSFET, tied with pins 1 and 2 to the source. |
| 4 | G | input | ESD-protected gate with an internal gate protection diode; VGSS is ±20 V and VGS(TH) is 1 V to 3 V. |
| 5 | D | passive | Drain of the N-channel MOSFET, tied with pins 6, 7 and 8 to the drain; VDSS is 60 V. |
| 6 | D | passive | Drain of the N-channel MOSFET, tied with pins 5, 7 and 8 to the drain; VDSS is 60 V. |
| 7 | D | passive | Drain of the N-channel MOSFET, tied with pins 5, 6 and 8 to the drain; VDSS is 60 V. |
| 8 | D | passive | Drain of the N-channel MOSFET, tied with pins 5, 6 and 7 to the drain; VDSS is 60 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS | 60 | V | 2 | |||
| Gate-Source Voltage | VGSS | -20 | 20 | V | 2 | ||
| Continuous Drain Current | ID | 12.1 | A | VGS = 10V, TA = +25°C (Note 6) | 2 | ||
| Continuous Drain Current | ID | 9.7 | A | VGS = 10V, TA = +70°C (Note 6) | 2 | ||
| Continuous Drain Current | ID | 28.9 | A | VGS = 10V, TC = +25°C (Note 6) | 2 | ||
| Pulsed Drain Current | IDM | 100 | A | 10µs Pulse, Duty Cycle = 1% | 2 | ||
| Maximum Continuous Body Diode Forward Current | IS | 20 | A | Note 6 | 2 | ||
| Pulsed Body Diode Forward Current | ISM | 100 | A | 10µs Pulse, Duty Cycle = 1% | 2 | ||
| Avalanche Current | IAS | 19 | A | L = 0.3mH | 2 | ||
| Avalanche Energy | EAS | 54.2 | A | L = 0.3mH | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 | ||
| Drain-Source Breakdown Voltage | BVDSS | 60 | V | VGS = 0V, ID = 1mA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | μA | VDS = 48V, VGS = 0V | 2 | ||
| Gate-Source Leakage | IGSS | -10 | 10 | μA | VGS = ±20V, VDS = 0V | 2 | |
| Gate Threshold Voltage | VGS(TH) | 1 | 3 | V | VDS = VGS, ID = 250μA | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 6.7 | 8.5 | mΩ | VGS = 10V, ID = 13.5A | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 8.9 | 12 | mΩ | VGS = 4.5V, ID = 11.5A | 2 | |
| Diode Forward Voltage | VSD | 0.9 | 1.2 | V | VGS = 0V, IS = 20A | 2 | |
| Total Power Dissipation | PD | 1.3 | W | Note 5 (FR-4, minimum recommended pad layout) | 2 | ||
| Thermal Resistance, Junction to Ambient | RJA | 93 | °C/W | Note 5 (FR-4, minimum recommended pad layout) | 2 | ||
| Total Power Dissipation | PD | 1.9 | W | Note 6 (FR-4, 1 inch square copper plate) | 2 | ||
| Thermal Resistance, Junction to Ambient | RθJA | 67 | °C/W | Note 6 (FR-4, 1 inch square copper plate) | 2 | ||
| Thermal Resistance, Junction to Case | RθJC | 11.7 | °C/W | Note 6 | 2 | ||
| Thermal Resistance, Junction to Ambient (transient thermal note) | RθJA | 98 | ℃/W | Figure 13 transient thermal resistance normalization note | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | IF = 15A, di/dt = 500A/μs Body Diode Reverse Recovery Charge QRR, 38.1, nC Notes: 5. Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. | 2 | |
| contacts | Copper | tin | Terminal Finish - Matte Tin Annealed over Copper Leadframe. | 1 |
CAD (KiCad official)
- Symbol:
DMT68M8LSS-13 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
dmt68m8lss-13-etched.step/dmt68m8lss-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmt68m8lss-13.step/dmt68m8lss-13.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (7 pp, sha256
42b4c82c7d002451, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DMT68M8LSS-13
**Diodes Incorporated** · MOSFETs · SO-8
DMT68M8LSS-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the N-channel MOSFET, tied with pins 2 and 3 to the source. |
| 2 | S | passive | Source of the N-channel MOSFET, tied with pins 1 and 3 to the source. |
| 3 | S | passive | Source of the N-channel MOSFET, tied with pins 1 and 2 to the source. |
| 4 | G | input | ESD-protected gate with an internal gate protection diode; VGSS is ±20 V and VGS(TH) is 1 V to 3 V. |
| 5 | D | passive | Drain of the N-channel MOSFET, tied with pins 6, 7 and 8 to the drain; VDSS is 60 V. |
| 6 | D | passive | Drain of the N-channel MOSFET, tied with pins 5, 7 and 8 to the drain; VDSS is 60 V. |
| 7 | D | passive | Drain of the N-channel MOSFET, tied with pins 5, 6 and 8 to the drain; VDSS is 60 V. |
| 8 | D | passive | Drain of the N-channel MOSFET, tied with pins 5, 6 and 7 to the drain; VDSS is 60 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS | | | 60 | V | | 2 |
| Gate-Source Voltage | VGSS | -20 | | 20 | V | | 2 |
| Continuous Drain Current | ID | | | 12.1 | A | VGS = 10V, TA = +25°C (Note 6) | 2 |
| Continuous Drain Current | ID | | | 9.7 | A | VGS = 10V, TA = +70°C (Note 6) | 2 |
| Continuous Drain Current | ID | | | 28.9 | A | VGS = 10V, TC = +25°C (Note 6) | 2 |
| Pulsed Drain Current | IDM | | | 100 | A | 10µs Pulse, Duty Cycle = 1% | 2 |
| Maximum Continuous Body Diode Forward Current | IS | | | 20 | A | Note 6 | 2 |
| Pulsed Body Diode Forward Current | ISM | | | 100 | A | 10µs Pulse, Duty Cycle = 1% | 2 |
| Avalanche Current | IAS | | | 19 | A | L = 0.3mH | 2 |
| Avalanche Energy | EAS | | | 54.2 | A | L = 0.3mH | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 | | 150 | °C | | 2 |
| Drain-Source Breakdown Voltage | BVDSS | 60 | | | V | VGS = 0V, ID = 1mA | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | 1 | μA | VDS = 48V, VGS = 0V | 2 |
| Gate-Source Leakage | IGSS | -10 | | 10 | μA | VGS = ±20V, VDS = 0V | 2 |
| Gate Threshold Voltage | VGS(TH) | 1 | | 3 | V | VDS = VGS, ID = 250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 6.7 | 8.5 | mΩ | VGS = 10V, ID = 13.5A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | | 8.9 | 12 | mΩ | VGS = 4.5V, ID = 11.5A | 2 |
| Diode Forward Voltage | VSD | | 0.9 | 1.2 | V | VGS = 0V, IS = 20A | 2 |
| Total Power Dissipation | PD | | 1.3 | | W | Note 5 (FR-4, minimum recommended pad layout) | 2 |
| Thermal Resistance, Junction to Ambient | RJA | | 93 | | °C/W | Note 5 (FR-4, minimum recommended pad layout) | 2 |
| Total Power Dissipation | PD | | 1.9 | | W | Note 6 (FR-4, 1 inch square copper plate) | 2 |
| Thermal Resistance, Junction to Ambient | RθJA | | 67 | | °C/W | Note 6 (FR-4, 1 inch square copper plate) | 2 |
| Thermal Resistance, Junction to Case | RθJC | | 11.7 | | °C/W | Note 6 | 2 |
| Thermal Resistance, Junction to Ambient (transient thermal note) | RθJA | | 98 | | ℃/W | Figure 13 transient thermal resistance normalization note | 5 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | | IF = 15A, di/dt = 500A/μs Body Diode Reverse Recovery Charge QRR, 38.1, nC Notes: 5. Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. | 2 |
| contacts | Copper | tin | Terminal Finish - Matte Tin Annealed over Copper Leadframe. | 1 |
## CAD (KiCad official)
- Symbol: `DMT68M8LSS-13`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `dmt68m8lss-13-etched.step` / `dmt68m8lss-13-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmt68m8lss-13.step` / `dmt68m8lss-13.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602948815607779328) (7 pp, sha256 `42b4c82c7d002451`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/dmt68m8lss-13-datasheet.pdf)