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DMT3020LSDQ-13

Public Made by Adom

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Diodes Incorporated MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttriode-mos tube-transistordmt3020lsdq-13factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

markdown

DMT3020LSDQ-13

Diodes Incorporated · MOSFETs · SO-8

DMT3020LSDQ-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of MOSFET 1 (N-channel, VDSS 30V).
2 G1 input Gate of MOSFET 1; gate-source voltage limit ±20V, threshold 1.0 to 2.5V.
3 S2 passive Source of MOSFET 2 (N-channel, VDSS 30V).
4 G2 input Gate of MOSFET 2; gate-source voltage limit ±20V, threshold 1.0 to 2.5V.
5 D2 passive Drain of MOSFET 2; 30V drain-source rating, 16A continuous at TC=+25°C.
6 D2 passive Drain of MOSFET 2; 30V drain-source rating, 16A continuous at TC=+25°C.
7 D1 passive Drain of MOSFET 1; 30V drain-source rating, 16A continuous at TC=+25°C.
8 D1 passive Drain of MOSFET 1; 30V drain-source rating, 16A continuous at TC=+25°C.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SO-8
Category Triode/MOS Tube/Transistor
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage BVDSS 30 V VGS = 0V, ID = 250μA 2
Zero Gate Voltage Drain Current IDSS 1 μA TJ = +25°C, VDS = 24V, VGS = 0V 2
Gate-Source Leakage IGSS -100 100 nA VGS = ±20V, VDS = 0V 2
Gate Threshold Voltage VGS(TH) 1 2.5 V VDS = VGS, ID = 250μA 2
Static Drain-Source On-Resistance (VGS=10V) RDS(ON) 14 20 mΩ VGS = 10V, ID = 9.0A 2
Static Drain-Source On-Resistance (VGS=4.5V) RDS(ON) 24 32 mΩ VGS = 4.5V, ID = 7.0A 2
Diode Forward Voltage VSD 0.8 1.2 V VGS = 0V, IS = 2A 2
Drain-Source Voltage VDSS 30 V TA = +25°C 2
Gate-Source Voltage VGSS -20 20 V TA = +25°C 2
Continuous Drain Current, TC = +25°C ID 16 A VGS = 10V, Steady State, Note 6 2
Continuous Drain Current, TC = +70°C ID 13 A VGS = 10V, Steady State, Note 6 2
Maximum Body Diode Forward Current IS 8 A Note 6 2
Pulsed Drain Current IDM 50 A 10μs Pulse, Duty Cycle = 1% 2
Pulsed Drain Body Diode Forward Current ISM 50 A 10μs Pulse, Duty Cycle = 1% 2
Avalanche Current IAS 13 A L = 0.1mH, Note 7 2
Avalanche Energy EAS 8.5 mJ L = 0.1mH, Note 7 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2
Total Power Dissipation (Note 5) PD 1 W TA = +25°C, minimum recommended pad layout 2
Thermal Resistance, Junction to Ambient (Note 5) RθJA 117 °C/W Steady State, Note 5 2
Total Power Dissipation (Note 6) PD 1.5 W TA = +25°C, 1inch square copper plate 2
Thermal Resistance, Junction to Ambient (Note 6) RθJA 81 °C/W Steady State, Note 6 2
Thermal Resistance, Junction to Case RθJC 20 °C/W Note 6 2
Input Capacitance Ciss 393 pF VDS = 15V, VGS = 0V, f = 1.0MHz 2
Output Capacitance Coss 173 pF VDS = 15V, VGS = 0V, f = 1.0MHz 2
Reverse Transfer Capacitance Crss 27 pF VDS = 15V, VGS = 0V, f = 1.0MHz 2
Gate Resistance Rg 1.1 Ω VDS = 0V, VGS = 0V, f = 1.0MHz 2
Total Gate Charge (VGS = 10V) Qg 7 nC VDD = 15V, ID = 9A 2
Total Gate Charge (VGS = 4.5V) Qg 3.6 nC VDD = 15V, ID = 9A 2
Gate-Source Charge Qgs 0.9 nC VDD = 15V, ID = 9A 2
Gate-Drain Charge Qgd 1.5 nC VDD = 15V, ID = 9A 2
Turn-On Delay Time tD(ON) 1.8 ns VDD = 15V, VGS = 10V, RG = 6Ω, ID = 9A 2
Turn-On Rise Time tR 1.9 ns VDD = 15V, VGS = 10V, RG = 6Ω, ID = 9A 2
Turn-Off Delay Time tD(OFF) 7.5 ns VDD = 15V, VGS = 10V, RG = 6Ω, ID = 9A 2
Turn-Off Fall Time tF 2.4 ns VDD = 15V, VGS = 10V, RG = 6Ω, ID = 9A 2
Reverse Recovery Time tRR 10 ns IF = 9A, dI/dt = 100A/μs 2
Reverse Recovery Charge QRR 2.6 nC IF = 9A, dI/dt = 100A/μs 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts Copper tin  Terminals Connections Indicator: See Diagram  Terminals: Finish - Matte Tin Annealed over Copper Lead 1

CAD (KiCad official)

  • Symbol: DMT3020LSDQ-13
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: dmt3020lsdq-13-etched.step / dmt3020lsdq-13-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dmt3020lsdq-13.step / dmt3020lsdq-13.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (7 pp, sha256 38a4105315dffa10, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF