# DMPH6050SSDQ-13

**Diodes Incorporated** · MOSFETs · SO-8

DMPH6050SSDQ-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of P-channel MOSFET 1; the MOSFET is rated for VDSS of -60V. |
| 2 | G1 | input | Gate of P-channel MOSFET 1; VGSS is rated at ±20V and the gate threshold is -1.0V to -3.0V. |
| 3 | S2 | passive | Source of P-channel MOSFET 2; the MOSFET is rated for VDSS of -60V. |
| 4 | G2 | input | Gate of P-channel MOSFET 2; VGSS is rated at ±20V and the gate threshold is -1.0V to -3.0V. |
| 5 | D2 | passive | Drain of P-channel MOSFET 2, connected to pin 6; continuous drain current is -5.2A at TA=+25°C with VGS=-10V. |
| 6 | D2 | passive | Drain of P-channel MOSFET 2, connected to pin 5; continuous drain current is -5.2A at TA=+25°C with VGS=-10V. |
| 7 | D1 | passive | Drain of P-channel MOSFET 1, connected to pin 8; continuous drain current is -5.2A at TA=+25°C with VGS=-10V. |
| 8 | D1 | passive | Drain of P-channel MOSFET 1, connected to pin 7; continuous drain current is -5.2A at TA=+25°C with VGS=-10V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SO-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | -60 |  |  | V | VGS = 0V, ID = -250μA | 2 |
| Zero Gate Voltage Drain Current (TJ = +25°C) | IDSS |  |  | -1 | µA | VDS = -60V, VGS = 0V | 2 |
| Gate-Source Leakage | IGSS | -100 |  | 100 | nA | VGS = ±20V, VDS = 0V | 2 |
| Gate Threshold Voltage | VGS(TH) | -1 |  | -3 | V | VDS = VGS, ID = -250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) |  | 34 | 48 | mΩ | VGS = -10V, ID = -5A | 2 |
| Static Drain-Source On-Resistance | RDS(ON) |  | 44 | 60 | mΩ | VGS = -4.5V, ID = -4A | 2 |
| Diode Forward Voltage | VSD |  | -0.7 | -1.2 | V | VGS = 0V, IS = -1A | 2 |
| Drain-Source Voltage | VDSS |  |  | -60 | V |  | 2 |
| Gate-Source Voltage | VGSS | -20 |  | 20 | V |  | 2 |
| Continuous Drain Current, TA = +25°C | ID |  |  | -5.2 | A | VGS = -10V, steady state, TA = +25°C | 2 |
| Continuous Drain Current, TA = +100°C | ID |  |  | -3.7 | A | VGS = -10V, steady state, TA = +100°C | 2 |
| Pulsed Drain Current | IDM |  |  | -35 | A | 10μs pulse, duty cycle = 1% | 2 |
| Maximum Continuous Body Diode Forward Current | IS |  |  | -2 | A | Note 7 | 2 |
| Avalanche Current | IAS |  |  | -25 | A | L = 0.1mH | 2 |
| Avalanche Energy | EAS |  |  | 33 | mJ | L = 0.1mH | 2 |
| Operating and Storage Temperature Range | TJ, TSTG | -55 |  | 175 | °C |  | 2 |
| Total Power Dissipation | PD |  | 1.5 |  | W | TA = +25°C, Note 6 (FR-4, minimum recommended pad layout) | 2 |
| Total Power Dissipation | PD |  | 2 |  | W | TA = +25°C, Note 7 (2oz copper, 1 inch square plate) | 2 |
| Thermal Resistance, Junction to Ambient, steady state | RθJA |  | 103 |  | °C/W | Note 6, steady state | 2 |
| Thermal Resistance, Junction to Ambient, t<10s | RθJA |  | 64 |  | °C/W | Note 6, t<10s | 2 |
| Thermal Resistance, Junction to Ambient, steady state | RθJA |  | 75 |  | °C/W | Note 7, steady state | 2 |
| Thermal Resistance, Junction to Ambient, t<10s | RθJA |  | 47 |  | °C/W | Note 7, t<10s | 2 |
| Thermal Resistance, Junction to Case | RθJC |  | 13 |  | °C/W | Note 7 | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC |  | Body Diode Reverse Recovery Charge QRR, 9.3, nC IF = -5A, di/dt = -100A/μs Notes: 6. Device mounted on FR-4 PC board, with minimum recommended pad layout, single sided. | 2 |
| contacts | Copper | tin |  Terminal Connections: See Diagram  Terminals: Finish, Matte Tin Annealed over Copper Leadframe | 1 |

## CAD (land: KiCad; 3D: generated from the datasheet)

- Symbol: `DMPH6050SSDQ-13`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8, generated on the KiCad land (body 3.85 x 4.9 mm, terminals on the pads, 1.45 mm tall, datasheet A, nominal). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
- 3D model files: `dmph6050ssdq-13-etched.step` / `dmph6050ssdq-13-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `dmph6050ssdq-13.step` / `dmph6050ssdq-13.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Diodes Incorporated datasheet](https://www.diodes.com/assets/Datasheets/DMPH6050SSDQ-13.pdf) (7 pp, sha256 `a79adf0f1cd60eeb`, retrieved 2026-11-13, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).

[Datasheet PDF](docs/dmph6050ssdq-13-datasheet.pdf)