component
DMP6110SVT-7
Public Made by Adomby adom
Diodes Incorporated Global Sourcing Parts, TSOT-26. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownDMP6110SVT-7
Diodes Incorporated · Global Sourcing Parts · TSOT-26
DMP6110SVT-7 from Diodes Incorporated, in a TSOT-26. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D | passive | Drain, internally connected to the other drain pins (2, 5, 6); VDSS is -60V and continuous ID is -7.3A at TC = +25°C with VGS = -10V. |
| 2 | D | passive | Drain, internally connected to the other drain pins (1, 5, 6); VDSS is -60V and IDM pulsed is -24A. |
| 3 | G | input | Gate; VGSS is ±20V maximum, with a gate threshold VGS(TH) of -1V to -3V at ID = -250µA. |
| 4 | S | passive | Source of the P-channel MOSFET; the body diode forward voltage is -1.2V maximum at IS = -1A. |
| 5 | D | passive | Drain, internally connected to the other drain pins (1, 2, 6); RDS(ON) is 105mΩ max at VGS = -10V, ID = -4.5A. |
| 6 | D | passive | Drain, internally connected to the other drain pins (1, 2, 5); RDS(ON) is 130mΩ max at VGS = -4.5V, ID = -3.5A. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | TSOT-26 |
| Category | Global Sourcing Parts |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | -60 | V | VGS = 0V, ID = -250µA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | -1 | µA | VDS = -48V, VGS = 0V | 2 | ||
| Gate-Source Leakage | IGSS | 100 | nA | VGS = ±16V, VDS = 0V | 2 | ||
| Gate Threshold Voltage | VGS(TH) | -1 | -3 | V | VDS = VGS, ID = -250µA | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 105 | mΩ | VGS = -10V, ID = -4.5A | 2 | ||
| Static Drain-Source On-Resistance | RDS(ON) | 130 | mΩ | VGS = -4.5V, ID = -3.5A | 2 | ||
| Diode Forward Voltage | VSD | -0.7 | -1.2 | V | VGS = 0V, IS = -1A | 2 | |
| Drain-Source Voltage | VDSS | -60 | V | 2 | |||
| Gate-Source Voltage | VGSS | -20 | 20 | V | 2 | ||
| Continuous Drain Current | ID | -7.3 | A | VGS = -10V, TC = +25°C | 2 | ||
| Continuous Drain Current | ID | -5.8 | A | VGS = -10V, TC = +70°C | 2 | ||
| Pulsed Drain Current | IDM | -24 | A | 380µs pulse, 1% duty cycle | 2 | ||
| Avalanche Current | IAS | -19 | A | L = 0.1mH | 2 | ||
| Repetitive Avalanche Energy | EAS | 18 | mJ | L = 0.1mH | 2 | ||
| Total Power Dissipation | PD | 1.2 | W | TA = +25°C; Note 5 (FR-4, minimum recommended pad layout) | 2 | ||
| Total Power Dissipation | PD | 0.75 | W | TA = +70°C; Note 5 | 2 | ||
| Total Power Dissipation | PD | 1.8 | W | TA = +25°C; Note 6 (FR-4, 1 inch square copper plate) | 2 | ||
| Total Power Dissipation | PD | 1.1 | W | TA = +70°C; Note 6 | 2 | ||
| Thermal Resistance, Junction to Ambient, steady state | RθJA | 105 | °C/W | Steady state; Note 5 | 2 | ||
| Thermal Resistance, Junction to Ambient, t<10s | RθJA | 60 | °C/W | t<10s; Note 5 | 2 | ||
| Thermal Resistance, Junction to Ambient, steady state | RθJA | 69 | °C/W | Steady state; Note 6 | 2 | ||
| Thermal Resistance, Junction to Ambient, t<10s | RθJA | 39 | °C/W | t<10s; Note 6 | 2 | ||
| Thermal Resistance, Junction to Case | RθJC | 15 | °C/W | Note 6 | 2 | ||
| Operating and Storage Temperature Range | TJ, TSTG | -55 | 150 | °C | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | Body Diode Reverse Recovery Charge QRR 6.18 nC Notes: 5. Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. | 2 | |
| contacts | Copper | tin | Terminal Connections Indicator: See Diagram Terminals: Finish Matte Tin Annealed over Copper Leadframe. | 1 |
CAD (KiCad official)
- Symbol:
DMP6110SVT-7 - Footprint:
Package_TO_SOT_SMD:TSOT-23-6 - 3D model: TSOT-26 (KiCad packages3D, STEP)
- 3D model files:
dmp6110svt-7-etched.step/dmp6110svt-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmp6110svt-7.step/dmp6110svt-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (7 pp, sha256
c42aefe50aa05c14, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).